Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection

AW Poon, X Luo, F Xu, H Chen - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
This paper reviews developments in cascaded microresonator-based matrix switches for
silicon photonic interconnection networks in many-core computing applications. Specifically …

Silicon photonics for extreme scale systems

Y Shen, X Meng, Q Cheng, S Rumley… - Journal of Lightwave …, 2019 - opg.optica.org
High-performance systems are increasingly bottlenecked by the growing energy and
communications costs of interconnecting numerous compute and memory resources …

A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip

H Gu, KH Mo, J Xu, W Zhang - 2009 IEEE Computer Society …, 2009 - ieeexplore.ieee.org
Networks-on-chip (NoCs) can improve the communication bandwidth and power efficiency
of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects …

Mode-division multiplexing for silicon photonic network-on-chip

X Wu, C Huang, K Xu, C Shu… - Journal of Lightwave …, 2017 - ieeexplore.ieee.org
Optical interconnect is a potential solution to attain the large bandwidth on-chip
communications needed in high-performance computers in a low-power and low-cost …

A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip

H Gu, J Xu, W Zhang - 2009 Design, Automation & Test in …, 2009 - ieeexplore.ieee.org
Multiprocessor system-on-chip (MPSoC) is an attractive platform for high-performance
applications. Networks-on-Chip (NoCs) can improve the on-chip communication bandwidth …

3-D mesh-based optical network-on-chip for multiprocessor system-on-chip

Y Ye, J Xu, B Huang, X Wu, W Zhang… - … on Computer-Aided …, 2013 - ieeexplore.ieee.org
Optical networks-on-chip (ONoCs) are emerging communication architectures that can
potentially offer ultrahigh communication bandwidth and low latency to multiprocessor …

Fault-tolerant routing mechanism in 3D optical network-on-chip based on node reuse

P Guo, W Hou, L Guo, W Sun, C Liu… - … on Parallel and …, 2019 - ieeexplore.ieee.org
The three-dimensional Network-on-Chips (3D NoCs) has become a mature multi-core
interconnection architecture in recent years. However, the traditional electrical lines have …

Comprehensive design space exploration of silicon photonic interconnects

M Bahadori, S Rumley, D Nikolova… - Journal of Lightwave …, 2016 - opg.optica.org
The paper presents a comprehensive physical layer design and modeling platform for
silicon photonic interconnects. The platform is based on explicit closed-form expressions for …

A generic optical router design for photonic network-on-chips

X Tan, M Yang, L Zhang, Y Jiang… - Journal of Lightwave …, 2011 - ieeexplore.ieee.org
Photonic network-on-chip (NoC) architectures are emerging as a new paradigm to
interconnect a large number of processing cores at chip level, meeting the pressing demand …

A hierarchical hybrid optical-electronic network-on-chip

KH Mo, Y Ye, X Wu, W Zhang, W Liu… - 2010 IEEE Computer …, 2010 - ieeexplore.ieee.org
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of
multiprocessor system-on-chip (MPSoC). However, traditional NoCs using metallic …