In this paper we present practical techniques that enable diagnosis of defective library cells
in a failing die. Our technique can handle large industrial designs and practical situations …

Earlier works showed that the resolution of defect diagnosis when multiple defects are
present in a chip can be improved by instructing the defect diagnosis procedure to ignore …

We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs).
Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our …

Experimental results indicate that the addition of diagnostic tests to a fault detection test set
may sometimes result in a larger set of candidate faults. Experimental results also indicate …

Some of the simplest and most effective fault diagnosis procedures for scan circuits use
scoring algorithms for associating a number, called a score, with every modeled fault they …

We describe a diagnostic test generation procedure that deals with the large numbers of
target fault pairs by considering subsets of faults. Each subset of faults is targeted separately …

A procedure for using fault dominance in a large volume diagnosis environment is
described. Fault dominance is shown to be useful for reducing the fault simulation time …

Πgora is an integration system for probabilistic data modelled using different formalisms
such as pc-tables, Bayesian networks, and stochastic automata. User queries are expressed …

Given a chip that produced a faulty output response to a test set, a defect diagnosis
procedure produces a set of candidate faults that is expected to identify the defects that are …

When multiple defects are present in a chip, the defects may be distributed randomly, or
clustered in certain areas. When a large number of defects are clustered in an area, the …