Analyses of static and dynamic random offset voltages in dynamic comparators

J He, S Zhan, D Chen, RL Geiger - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
When mismatches are present in a dynamic comparator, due to internal positive feedback
and transient response, it is always challenging to analytically predict the input-referred …

[图书][B] Circuit techniques for low-voltage and high-speed A/D converters

ME Waltari, KAI Halonen - 2002 - books.google.com
For four decades the evolution of integrated circuits has followed Moore's law, according to
which the number of transistors per square millimeter of silicon doubles every 18 months. At …

Compact low-power impedance-to-digital converter for sensor array microsystems

C Yang, SR Jadhav, RM Worden… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
With the rapid progress in CMOS compatible microfabrication of biosensors, there is an
emerging need to miniaturize biosensor arrays onto the surface of silicon chips that acquire …

A low-power low-offset dynamic comparator for analog to digital converters

M Hassanpourghadi, M Zamani, M Sharifkhani - Microelectronics Journal, 2014 - Elsevier
A comparator comprises a cross coupled circuit which produces a positive feedback. In
conventional comparators, the mismatch between the cross coupled circuits determines the …

A novel low offset low power CMOS dynamic comparator

PP Gandhi, NM Devashrayee - Analog Integrated Circuits and Signal …, 2018 - Springer
This paper presents a novel fully dynamic double tail dynamic comparator that exhibits low
offset voltage compared to the traditional dynamic comparators. This paper comprises a …

Towards High Throughput Cell Growth Screening: A New CMOS 8 8 Biosensor Array for Life Science Applications

G Nabovati, E Ghafar-Zadeh… - IEEE transactions on …, 2016 - ieeexplore.ieee.org
In this paper we present a CMOS capacitive sensor array as a compact and low-cost
platform for high-throughput cell growth monitoring. The proposed biosensor, consists of an …

[图书][B] Pipelined ADC design and enhancement techniques

I Ahmed - 2010 - books.google.com
Pipelined ADCs have seen phenomenal improvements in performance over the last few
years. As such, when designing a pipelined ADC a clear understanding of the design …

A 25 MHz bandwidth 5th-order continuous-time low-pass sigma-delta modulator with 67.7 dB SNDR using time-domain quantization and feedback

CY Lu, M Onabajo, V Gadde, YC Lo… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper introduces a continuous-time low-pass sigma-delta modulator operating with a
seven-phase 400 \, MHz clocking scheme to control time-based processing in the 3-bit two …

In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies

HE Barkam, S Yun, PR Genssler, CK Liu… - … on Circuits and …, 2024 - ieeexplore.ieee.org
Novel computer architectures like Compute-in-Memory (CiM) merge the memory and
processing units, mimicking the human brain. Simultaneously, Hyperdimensional …

A 50-MS/s (35 mW) to 1-kS/s (15/spl mu/W) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

I Ahmed, DA Johns - IEEE journal of solid-state circuits, 2005 - ieeexplore.ieee.org
A novel rapid power-on operational amplifier and a current modulation technique are used
in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-/spl mu/m CMOS to realize power scalability …