Low-power high-frequency phase frequency detector for minimal blind-zone phase-locked loops
This paper describes a symmetric phase frequency detector (PFD). The symmetric structure
of PFD provides phase-locked loop (PLL) functions with a low jitter. The most important point …
of PFD provides phase-locked loop (PLL) functions with a low jitter. The most important point …
All-digital delay-locked loop for 3D-IC die-to-die clock synchronization
CC Chung, CY Hou - … of 2014 International Symposium on VLSI …, 2014 - ieeexplore.ieee.org
In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock
synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can …
synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can …
A novel charge pump with low current for low-power delay-locked loops
M Estebsari, M Gholami… - Circuits, systems, and …, 2017 - Springer
In this paper, a new charge pump circuit for reducing charge and discharge currents with low
power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump …
power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump …
Resource allocation and design techniques of prebond testable 3-D clock tree
TY Kim, T Kim - IEEE Transactions on Computer-Aided Design …, 2012 - ieeexplore.ieee.org
In 3-D stacked integrated circuit (IC) manufacturing, for the acceptable high yield, it is
essential to stack only known good dies by testing the individual dies at the prebond stage …
essential to stack only known good dies by testing the individual dies at the prebond stage …
An all-digital on-chip jitter measurement circuit in 65nm CMOS technology
CC Chung, WJ Chu - … of 2011 International Symposium on VLSI …, 2011 - ieeexplore.ieee.org
An all-digital built-in jitter measurement (BIJM) circuit is presented in this paper. A frequency
divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a …
divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a …
[图书][B] Single event transient modeling and mitigation techniques for mixed-signal delay locked loop (DLL) and clock circuits
P Maillard - 2014 - search.proquest.com
SINGLE EVENT TRANSIENT MODELING AND MITIGATION TECHNIQUES FOR MIXED-SIGNAL
DELAY LOCKED LOOP (DLL) AND CLOCK CIRCUITS By Pierre Page 1 SINGLE EVENT …
DELAY LOCKED LOOP (DLL) AND CLOCK CIRCUITS By Pierre Page 1 SINGLE EVENT …
A multi-modulus fractional divider with TDC free calibration scheme for mitigation of TX-VCO pulling
L Liu, J Jin, X Liu, J Zhou - … on Circuits and Systems II: Express …, 2020 - ieeexplore.ieee.org
This presents a novel fractional local oscillator (LO) divider with an area-efficient calibration
scheme to mitigate oscillator pulling effects in transmitter (TX) by offsetting the LO and TX …
scheme to mitigate oscillator pulling effects in transmitter (TX) by offsetting the LO and TX …
An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units
W Wang, H Zhou, F Ye, J Ren - 2015 IEEE 11th International …, 2015 - ieeexplore.ieee.org
To meet the rapidly growing demands of ADC speed and resolution, time-interleaved ADC
(TI-ADC) is one of the hot topics. However, there are intrinsic problems such as clock skew …
(TI-ADC) is one of the hot topics. However, there are intrinsic problems such as clock skew …
Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit
R Yeniçeri, ME Yalçın - International Journal of Circuit Theory …, 2016 - Wiley Online Library
In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay
in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice …
in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice …
Design of low power, low jitter DLL tested at all five corners to avoid false locking
HS Raghav, S Maheshwari… - 2012 10th IEEE …, 2012 - ieeexplore.ieee.org
A modified Phase Selection Circuit, a modified Phase Frequency Detector and a modified
Voltage Controlled Delay Line is proposed to improve the Delay Locked Loops (DLL) …
Voltage Controlled Delay Line is proposed to improve the Delay Locked Loops (DLL) …