Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers

O Akbari, M Kamal, A Afzali-Kusha… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
In this paper, we propose four 4: 2 compressors, which have the flexibility of switching
between the exact and approximate operating modes. In the approximate mode, these dual …

Approximate multiplier design using novel dual-stage 4: 2 compressors

PJ Edavoor, S Raveendran, AD Rahulkar - IEEE Access, 2020 - ieeexplore.ieee.org
High speed multimedia applications have paved way for a whole new area in high speed
error-tolerant circuits with approximate computing. These applications deliver high …

A Reduced-sp- Adder-Based High Frequency Bit Multiplier Using Dadda Algorithm

Z Shabbir, AR Ghumman, SM Chaudhry - Circuits, Systems, and Signal …, 2016 - Springer
A low-power, high-speed 4 * 4 4× 4 multiplier using Dadda algorithm is proposed. The full
adder blocks used in this multiplier have been designed using reduced-split precharge-data …

High accurate multipliers using new set of approximate compressors

S Shirzadeh, B Forouzandeh - AEU-International Journal of Electronics …, 2021 - Elsevier
Approximate multipliers play vital role in the error-resilience applications by balancing
accuracy and power efficiency. In this article, we improved the accuracy of approximate …

High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

KK Padmanabhan, U Seerengasamy, AS Ponraj - Electronics, 2022 - mdpi.com
In the computation systems that are frequently utilized in Digital Signal Processing (DSP)-
and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role …

Fast energy efficient radix-16 sequential multiplier

S Amanollahi, G Jaberipur - IEEE Embedded Systems Letters, 2017 - ieeexplore.ieee.org
We propose a new sequential multiplier design that generates the radix-16 partial products
(eg, F) as two high (H) and low (L) components, such that F= 4H+ L, H, L∈{0, 1, 2, 3}× X …

[PDF][PDF] A novel approach of multiplier design based on BCD decoder

S Alkurwy - Indonesian Journal of Electrical Engineering and …, 2019 - researchgate.net
A novel approach of multiplier design is presented in this paper. The design idea is
implemented based on binary coded decimal (BCD) decoder to seven segment display, by …

Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach

BG Gowda, HC Prashanth… - … on Quality Electronic …, 2024 - ieeexplore.ieee.org
Approximation in arithmetic computations is accepted widely in error-resilient image and
signal processing applications, in which the computation time is more critical than accuracy …

Design of multiplier with dual mode based approximate full adder

KS Nandam, K Jamal, AK Budati… - 2020 5th …, 2020 - ieeexplore.ieee.org
The CSL (Carry Select) adder is among the best adders to perform adequate arithmetic
operations for several architectures. The structure of the CSL adder is so significant that it …

A study of signed multipliers on FPGAs

M Aly, A Sayed - 2012 IEEE International Conference on …, 2012 - ieeexplore.ieee.org
Multiplication is an important fundamental operation that is critical in most signal and image
processing applications. It is also essential for all types of wireless communications …