Defect and microstructural evolution in thermally cycled Cu through-silicon vias

J Marro, C Okoro, Y Obeng, K Richardson - Microelectronics Reliability, 2014 - Elsevier
In this study, the effect of thermal cycling on defect generation, microstructure, and RF signal
integrity of blind Cu through-silicon vias (TSVs) were investigated. Three different thermal …

Post-bond test of Through-Silicon Vias with open defects

R Rodríguez-Montañés, D Arumí… - 2014 19th IEEE …, 2014 - ieeexplore.ieee.org
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-
D ICs) and are susceptible to undergo defects at different stages: during their own …

Defect detection method for 3D chip and system using the same

YJ Huang, CL Pan, SC Lin, MH Guo - US Patent 10,303,823, 2019 - Google Patents
A defect detection method for a 3D chip and a system using the same are provided. The
method includes: generating a plurality of physical models having a defect of at least one …

Postbond test of through-silicon vias with resistive open defects

R Rodríguez-Montañés, D Arumí… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve
high bandwidth, and short interconnect delays in nanometer three-dimensional integrated …

High-frequency measurements of TSV failures

J Kim, D Jung, J Cho, JS Pak, JM Yook… - 2012 IEEE 62nd …, 2012 - ieeexplore.ieee.org
Due to a lot of thermal and mechanical loads during TSV process or post TSV process such
as metallization and die stacking, disconnection failure can occur which results in 3D IC …

Understanding early failure behavior in 3D-interconnects: Empirical modeling of broadband signal losses in TSV-enabled interconnects

KJ Coakley, P Kabos, S Moreau… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
We develop an empirical model for measured frequency-dependent insertion loss (). The
model parameters are determined with a stochastic optimization implementation of the …

Oscillation-based technique for TSV post-bond test considerations

SG Papadopoulos, V Gerakis… - 2017 6th International …, 2017 - ieeexplore.ieee.org
Through Silicon VIAs (TSVs) are critical elements in three dimensional integrated circuits
(3D ICs). Various defects may occur during their fabrication process, the bonding stage or …

Disconnection failure model and analysis of TSV-based 3D ICs

DH Jung, J Kim, H Kim, JJ Kim, J Kim… - 2012 IEEE Electrical …, 2012 - ieeexplore.ieee.org
The trend in semiconductor industry is rapidly shifting from 2-dimension to 3-dimension to
satisfy the ever-growing demand on the miniaturization of electronic devices. The …

Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs

SG Papadopoulos, V Gerakis… - … on Power and …, 2017 - ieeexplore.ieee.org
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of
three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern …

A post-bond TSVs test solution for leakage fault

Y Yu, Z Yang, K Xu - … International Test Conference in Asia (ITC …, 2019 - ieeexplore.ieee.org
During the 3-D ICs manufacturing process, TSVs are susceptible to undergo different faults.
Among these faults, the leakage fault is one of the most common cases. In this paper, a new …