A comparative study of predictable dram controllers
Recently, the research community has introduced several predictable dynamic random-
access memory (DRAM) controller designs that provide improved worst-case timing …
access memory (DRAM) controller designs that provide improved worst-case timing …
MCXplore: Automating the validation process of DRAM memory controller designs
We present an automated framework for the validation of memory controllers (MCs) called
MCXplore. In developing this framework, we construct formal models for memory requests …
MCXplore. In developing this framework, we construct formal models for memory requests …
An expert system for checking the correctness of memory systems using simulation and metamorphic testing
During the last few years, computer performance has reached a turning point where
computing power is no longer the only important concern. This way, the emphasis is shifting …
computing power is no longer the only important concern. This way, the emphasis is shifting …
A Coq framework for more trustworthy DRAM controllers
F Lisboa Malaquias, M Asavoae… - Proceedings of the 30th …, 2022 - dl.acm.org
In order to prove conformance to memory standards and bound memory access latency,
recently proposed real-time DRAM controllers rely on paper and pencil proofs, which can be …
recently proposed real-time DRAM controllers rely on paper and pencil proofs, which can be …
A formal framework to design and prove trustworthy memory controllers
F Lisboa Malaquias, M Asavoae, F Brandner - Real-Time Systems, 2023 - Springer
In order to prove conformance to memory standards and bound memory access latency,
recently proposed real-time DRAM controllers rely on paper and pencil proofs, which can be …
recently proposed real-time DRAM controllers rely on paper and pencil proofs, which can be …
Fast validation of DRAM protocols with timed petri nets
In recent years, an increasing number of different JEDEC memory standards, like DDR4/5,
LPDDR4/5, GDDR6, Wide I/O2, HBM2, and NVDIMM-P have been specified, which differ …
LPDDR4/5, GDDR6, Wide I/O2, HBM2, and NVDIMM-P have been specified, which differ …
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems
A memory controller manages the flow of data to and from attached memory devices. The
order in which a set of contending memory requests from different tasks are serviced …
order in which a set of contending memory requests from different tasks are serviced …
From the Standards to Silicon: Formally Proved Memory Controllers
FL Malaquias, M Asavoae, F Brandner - NASA Formal Methods …, 2023 - Springer
Recent research in both academia and industry has successfully used deductive verification
to design hardware and prove its correctness. While tools and languages to write formally …
to design hardware and prove its correctness. While tools and languages to write formally …
Predictable shared memory resources for multi-core real-time systems
M Hassan - 2017 - uwspace.uwaterloo.ca
A major challenge in multi-core real-time systems is the interference problem on the shared
hardware components amongst cores. Examples of these shared components include …
hardware components amongst cores. Examples of these shared components include …
PMSMC: Priority-based multi-requestor scheduler for embedded system memory controller
Abstract Modern Multi-Processor System-On-Chips (MPSOC) are widely used especially in
real-time embedded systems due to their high throughput and low per unit cost. However …
real-time embedded systems due to their high throughput and low per unit cost. However …