A smart memory computing system that uses smart memory for massive data storage as well
as for massive parallel execution is disclosed. The data stored in the smart memory can be …

A smart memory computing system that uses smart memory for massive data storage as well
as for massive parallel execution is disclosed. The data stored in the smart memory can be …

806 having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local
memory devices attached to the card, and a buffer device attached to the card, the buffer …

US PATENT DOCUMENTS 6,219,760 B1 4/2001 McMinn 6,233,639 B1 5/2001 Dell et al.
4,641,263. A 2f1987 Perlman et al. 6,260,127 B1 7/2001 Olarig et al................. 711/167 …

Apparatus and methods are disclosed for adjusting phase of data signals to compensate for
phase-offset variations between devices during normal operation. The phase of data signals …

(57) ABSTRACT A high density high reliability memory module with power gating and a fault
tolerant address and command bus. The memory module includes a rectangular printed …

A configuration register used to adjust a clock or request signal with respect to the other.
Specifically, a look-up table is provided in the memory controller. The look-up table is filled …

Abstract Systems and methods for generating write data signals having variable delays for
use in write operations to memory components are provided. These memory systems and …

A method for programming a controller of a memory unit has been developed. The method
includes inputting variable initialization parameters of the memory unit and a clock delay …

A module having first and second memory devices and a termination component. A first
signal line is coupled to the first memory device to provide first data thereto, the first data to …