Modeling single event transients in advanced devices and ICs
The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs)
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …
Single-event transient modeling in a 65-nm bulk CMOS technology based on multi-physical approach and electrical simulations
This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and
electrical simulations (CADENCE tool). The method is validated by SET measurements on …
electrical simulations (CADENCE tool). The method is validated by SET measurements on …
Simulation study of the layout technique for P-hit single-event transient mitigation via the source isolation
J Chen, S Chen, B Liang, B Liu - IEEE Transactions on Device …, 2012 - ieeexplore.ieee.org
In this paper, a layout technique for P-hit single-event transient (SET) mitigation via source
isolation is studied by way of technology-computer-aided-design numerical simulations. The …
isolation is studied by way of technology-computer-aided-design numerical simulations. The …
A physics-based single event transient pulse width model for CMOS VLSI circuits
The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-
50 nm CMOS VLSI circuits. These transients are easily captured and propagated in high …
50 nm CMOS VLSI circuits. These transients are easily captured and propagated in high …
Single-event upset characterization across temperature and supply voltage for a 20-nm bulk planar CMOS technology
JS Kauppila, WH Kay, TD Haeffner… - … on Nuclear Science, 2015 - ieeexplore.ieee.org
Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over
temperature and voltage supply variations in a 20-nm bulk planar complementary metal …
temperature and voltage supply variations in a 20-nm bulk planar complementary metal …
Comparative soft error evaluation of layout cells in FinFET technology
This work presents a comparative soft error evaluation of logic gates in bulk FinFET
technology from 65-down to 32-nm technology generations. Single Event Transients …
technology from 65-down to 32-nm technology generations. Single Event Transients …
Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology
Radiation-induced soft error is an ever-increasing concern in the microelectronic industry in
order to provide reliable VLSI systems at advanced technology nodes. Most of the …
order to provide reliable VLSI systems at advanced technology nodes. Most of the …
A 65 nm temporally hardened flip-flop circuit
A guard-gate based flip-flop circuit temporally hardened against single-event effects is
presented in this paper. Compared to several existed techniques, the organization of …
presented in this paper. Compared to several existed techniques, the organization of …
Characterization of the effect of pulse quenching on single-event transients in 65-nm twin-well and triple-well CMOS technologies
J Chen, J Yu, P Yu, B Liang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
As chip technologies scale down in size, multiple adjacent logic nodes are often affected by
a single high-energy ion strike. The so-called pulse quenching effect, induced by single …
a single high-energy ion strike. The so-called pulse quenching effect, induced by single …
[HTML][HTML] An infrastructure for accurate characterization of single-event transients in digital circuits
VS Veeravalli, T Polzer, U Schmid, A Steininger… - Microprocessors and …, 2013 - Elsevier
We present the architecture and a detailed pre-fabrication analysis of a digital measurement
ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also …
ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also …