Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial

B Casper, F O'Mahony - … Transactions on Circuits and Systems I …, 2009 - ieeexplore.ieee.org
The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

[图书][B] Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy

JD Cressler, S Monfray, G Freeman, D Friedman… - 2018 - taylorfrancis.com
An extraordinary combination of material science, manufacturing processes, and innovative
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …

Analysis of charge-pump phase-locked loops

PK Hanumolu, M Brownlee… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
In this paper, we present an exact analysis for third-order charge-pump phase-locked loops
using state equations. Both the large-signal lock acquisition process and the small-signal …

[PDF][PDF] Designing bang-bang PLLs for clock and data recovery in serial data transmission systems

RC Walker - Phase-Locking in High-Performance Systems, 2003 - omnisterra.com
Clock recovery using phase-locked loops (PLL) with binary (bang-bang) or ternary-
quantized phase detectors has become increasingly common starting with the advent of fully …

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

JS Rieh, B Jagannathan, DR Greenberg… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
The relatively less exploited terahertz band possesses great potential for a variety of
important applications, including communication applications that would benefit from the …

A 9.8-11.5-GHz quadrature ring oscillator for optical receivers

JD Van der Tang, D Kasperkovitz… - IEEE Journal of solid …, 2002 - ieeexplore.ieee.org
This paper describes a quadrature ring oscillator that is tunable from 9.8 to 11.5 GHz in a 30-
GHz f/sub T/BiCMOS technology. The ring oscillator can be used in advanced data clock …

[图书][B] CMOS Analog Integrated Circuits

T Ndjountche - 2019 - api.taylorfrancis.com
Hardware developments have been a major vehicle in popularizing the applications of
signal processing theory in both science and engineering. The book describes the important …

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

SJ Song, SM Park, HJ Yoo - IEEE Journal of Solid-State …, 2003 - ieeexplore.ieee.org
A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS
technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a …

A 2.5-Gb/s Multi-Rate 0.25-m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency …

MH Perrott, Y Huang, RT Baird… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
A 0.25-mum CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique
analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated …

SiGe BiCMOS integrated circuits for high-speed serial communication links

DJ Friedman, M Meghelli, BD Parker… - IBM Journal of …, 2003 - ieeexplore.ieee.org
Considerable progress has been made in integrating multi-Gb/s functions into silicon chips
for data-and telecommunication applications. This paper reviews the key requirements for …