Strong authentication for RFID systems using the AES algorithm
M Feldhofer, S Dominikus, J Wolkerstorfer - … MA, USA, August 11-13, 2004 …, 2004 - Springer
Radio frequency identification (RFID) is an emerging technology which brings enormous
productivity benefits in applications where objects have to be identified automatically. This …
productivity benefits in applications where objects have to be identified automatically. This …
Scan based side channel attack on dedicated hardware implementations of data encryption standard
Scan based test is a double edged sword. On one hand, it is a powerful test technique. On
the other hand, it is an equally powerful attack tool. We show that scan chains can be used …
the other hand, it is an equally powerful attack tool. We show that scan chains can be used …
Very compact FPGA implementation of the AES algorithm
P Chodowiec, K Gaj - … on cryptographic hardware and embedded systems, 2003 - Springer
In this paper a compact FPGA architecture for the AES algorithm with 128-bitkey targeted for
low-costembedded applications is presented. Encryption, decryption and key schedule are …
low-costembedded applications is presented. Encryption, decryption and key schedule are …
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
We provide an overview of selected crypto‐hardware devices, with a special reference to the
lightweight electronic implementation of encryption/decryption schemes, hash functions, and …
lightweight electronic implementation of encryption/decryption schemes, hash functions, and …
AES implementation on a grain of sand
M Feldhofer, J Wolkerstorfer, V Rijmen - IEE Proceedings-Information Security, 2005 - IET
The authors present a hardware implementation of the advanced encryption standard (AES)
which is optimised for low-resource requirements. The standard-cell implementation on a …
which is optimised for low-resource requirements. The standard-cell implementation on a …
A 21.54 Gbits/s fully pipelined AES processor on FPGA
A Hodjat, I Verbauwhede - 12th annual IEEE symposium on …, 2004 - ieeexplore.ieee.org
This paper presents the architecture of a fully pipelined AES encryption processor on a
single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining …
single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining …
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture
S Morioka, A Satoh - IEEE Transactions on Very Large Scale …, 2004 - ieeexplore.ieee.org
In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl
mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all …
mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all …
Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors
A Hodjat, I Verbauwhede - IEEE Transactions on Computers, 2006 - ieeexplore.ieee.org
This paper explores the area-throughput trade-off for an ASIC implementation of the
advanced encryption standard (AES). Different pipelined implementations of the AES …
advanced encryption standard (AES). Different pipelined implementations of the AES …
Parallel AES encryption engines for many-core processor arrays
By exploring different granularities of data-level and task-level parallelism, we map 16
implementations of an Advanced Encryption Standard (AES) cipher with both online and …
implementations of an Advanced Encryption Standard (AES) cipher with both online and …
[图书][B] Wireless security and cryptography: specifications and implementations
As the use of wireless devices becomes widespread, so does the need for strong and
secure transport protocols. Even with this intensified need for securing systems, using …
secure transport protocols. Even with this intensified need for securing systems, using …