High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects
JH Chae - IEEE Open Journal of the Solid-State Circuits …, 2024 - ieeexplore.ieee.org
Currently, we are living in a data-centric era as the need for large amounts of data has
dramatically increased due to the widespread adoption of artificial intelligence (AI) in a …
dramatically increased due to the widespread adoption of artificial intelligence (AI) in a …
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces
This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4)
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces
A single-ended transmitter achieves low power consumption with an integrated voltage
modulation (IVM) scheme for memory interfaces. The transmitter preserves the power …
modulation (IVM) scheme for memory interfaces. The transmitter preserves the power …
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces
This article presents a low-power and jitter-filtering-capable clock distribution scheme using
a digital phase-locked loop-based (DPLL-based) quadrature clock generator (QCG) for high …
a digital phase-locked loop-based (DPLL-based) quadrature clock generator (QCG) for high …
25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies
C Han, KS Lee, JH Chae - IEEE Journal of Solid-State Circuits, 2024 - ieeexplore.ieee.org
We present an NRZ/PAM-3 dual-mode transmitter featuring a 9-bit/6-UI-based embedded
partial data bus inversion (pDBI). In this design, if the number of “1” s exceeds three in the …
partial data bus inversion (pDBI). In this design, if the number of “1” s exceeds three in the …
Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing
S Lim, IJ Jung, GS Kim, DH Ko, S Lee… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
Dynamic random access memory (DRAM) sensing capabilities have deteriorated with the
reduced supply voltage and cell capacitance as the DRAM process scales down. Previous …
reduced supply voltage and cell capacitance as the DRAM process scales down. Previous …
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications
For low-power 8.5-Gbps operation, 4th-generation 10-nm 16-Gb LPDDR5x DRAM I/O
circuits and control methods are proposed in this article. The proposed I/O improves signal …
circuits and control methods are proposed in this article. The proposed I/O improves signal …
13.8 A 1a-nm 1.05 V 10.5 Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance …
Y Seo, J Choi, S Cho, H Han, W Kim… - … Solid-State Circuits …, 2024 - ieeexplore.ieee.org
The LPDDR product family originally sought to minimize power consumption. As the
LPDDR5X is released with a 33% increase in maximum operating speed, low-power and …
LPDDR5X is released with a 33% increase in maximum operating speed, low-power and …
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude-Detection LSB Decoder for Memory Interfaces
This study proposes a power-efficient 28-Gb/s single-ended four-level pulse amplitude
modulation (PAM-4) transceiver (TRX) for next-generation memory interfaces. In the …
modulation (PAM-4) transceiver (TRX) for next-generation memory interfaces. In the …
Defect-based empirical model for on-state degradation in sub-20-nm DRAM periphery pFETs under arbitrary condition
D Wang, L Zhou, Y Xue, P Ren, L Zhang… - … on Electron Devices, 2022 - ieeexplore.ieee.org
This work investigates the ON-state degradation under arbitrary stress conditions for
periphery pFETs fabricated in the sub-20-nm DRAM technology. Three types of traps are …
periphery pFETs fabricated in the sub-20-nm DRAM technology. Three types of traps are …