Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods
The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …
Aging-and variation-aware delay monitoring using representative critical path selection
Process together with runtime variations in temperature and voltage, as well as transistor
aging, degrade path delay and may eventually induce circuit failure due to timing variations …
aging, degrade path delay and may eventually induce circuit failure due to timing variations …
Performance screening using functional path ring oscillators
T Kilian, D Tille, M Huch, M Hanel… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The testing of integrated circuits is an important topic, particularly in safety-critical
applications. This is especially true for microcontrollers (MCUs) used in the automotive …
applications. This is especially true for microcontrollers (MCUs) used in the automotive …
Characterizing bti and hcd in 1.2 v 65nm cmos oscillators made from combinational standard cells and processor logic paths
VM Van Santen, JM Gata-Romero… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
Bias Temperature Instability (BTI) and Hot-Carrier Degradation (HCD) are key aging
mechanisms, frequently studied with transistor measurements or inverter-based (INV) Ring …
mechanisms, frequently studied with transistor measurements or inverter-based (INV) Ring …
A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs
M Sadi, L Winemberg… - 2015 IEEE 33rd VLSI Test …, 2015 - ieeexplore.ieee.org
Because of process variations, the post-silicon critical or near-critical paths differ from those
identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack …
identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack …
EffiTest2: Efficient delay test and prediction for post-silicon clock skew configuration under process variations
At nanometer manufacturing technology nodes, process variations affect circuit performance
significantly. This trend leads to a large timing margin and thus overdesign in the traditional …
significantly. This trend leads to a large timing margin and thus overdesign in the traditional …
Prognosis of NBTI aging using a machine learning scheme
Circuit aging is an important failure mechanism in nanoscale designs and is a growing
concern for the reliability of future systems. Aging results in circuit performance degradation …
concern for the reliability of future systems. Aging results in circuit performance degradation …
Aging-Aware Critical Path Selection via Graph Attention Networks
In advanced technology nodes, aging effects like negative and positive bias temperature
instability (NBTI and PBTI) become increasingly significant, making timing closure and …
instability (NBTI and PBTI) become increasingly significant, making timing closure and …
Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors
Y Zhao, HG Kerkhoff - 2016 IEEE 25th Asian test symposium …, 2016 - ieeexplore.ieee.org
This paper describes the usage of IDDX monitors, which provide (periodic) data to be
employed for predicting the remaining life-time of processor cores in homogeneous multi …
employed for predicting the remaining life-time of processor cores in homogeneous multi …
A 3D Virtual Classroom Simulation for Supporting School Teachers Training Based on Synectics-" Making the Strange Familiar"
P Kallonis, DG Sampson - 2011 IEEE 11th International …, 2011 - ieeexplore.ieee.org
The possible exploitation of 3D Virtual Worlds (VW) remains a major challenge for school
teachers, since 3D VWs introduce new concepts that even teachers who are experienced …
teachers, since 3D VWs introduce new concepts that even teachers who are experienced …