Design of resistive load inverter and common source amplifier circuits using symmetric and asymmetric nanowire FETs
VB Sreenivasulu, NA Kumari, V Lokesh… - Journal of Electronic …, 2023 - Springer
In this paper, multi-channel nanowire (NW) performance is significantly improved by
symmetric and asymmetric spacer length optimization. Device performance metrics …
symmetric and asymmetric spacer length optimization. Device performance metrics …
Nanosheet FET for Future Technology Scaling
AS Kumar, VB Sreenivasulu… - … Devices for Artificial …, 2024 - Wiley Online Library
Improvements in the VLSI industry have always been striving to justify the Moore's law by
implanting, twice count transistors from the existing one. This law has made a significant …
implanting, twice count transistors from the existing one. This law has made a significant …
Gate stack analysis of nanosheet FET for analog and digital circuit applications
NA Kumari, V Vijayvargiya, AK Upadhyay… - ECS Journal of Solid …, 2023 - iopscience.iop.org
This manuscript demonstrates the performance comparison of vertically stacked nanosheet
FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric …
FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric …
Innovative Spacer material integration in Tree-FETs for enhanced performance across Variable channel lengths
D Parvathi, P Prithvi - Micro and Nanostructures, 2024 - Elsevier
This work presents a novel three-channel Tree-FET optimized for superior DC and analog
performance metrics. The device structure features nanosheets with a width (NS WD) of 9 …
performance metrics. The device structure features nanosheets with a width (NS WD) of 9 …
Design and Analysis of dual-k spacer CombFET for Digital and Synaptic Applications
NA Kumari, SR Karumuri, J Ajayan… - IEEE …, 2024 - ieeexplore.ieee.org
This paper delves into the burgeoning realm of CombFETs, offering a comprehensive
analysis of their structural design, simulation methodologies, and performance …
analysis of their structural design, simulation methodologies, and performance …
Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications
AK Panigrahy, VVS Amudalapalli, DS Rani… - IEEE …, 2024 - ieeexplore.ieee.org
This work investigates the effect of single and dual-k spacer materials consisting of different
dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) …
dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) …
Impact of ambient temperature on CombFET for sub-5-nm technology nodes: An RF performance perspective
P Srinivas, NA Kumari, A Kumar, PK Tiwari… - Microsystem …, 2024 - Springer
This paper explores the impact of ambient temperature on the RF performance parameters
of CombFET device. The CombFET has been considered one of the most realistic …
of CombFET device. The CombFET has been considered one of the most realistic …