(57) ABSTRACT A latency control circuit includes a delay unit configured to delay an input
signal for a delay corresponding to a phase difference between an external clock and an …

Apparatuses and methods related to adjusting a delay of a command signal path are
disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that …

A read latency control circuit is described having a clock synchronization circuit and a read
latency control circuit. The clock synchronization circuit includes an adjustable delay line to …

Apparatuses and methods for indirect phase variation detec tion are disclosed herein. An
example apparatus may include a clock generator circuit comprising a delay-locked loop …

Apparatuses for controlling latencies on input signal paths in semiconductor devices are
disclosed. An example apparatus includes: a clock input buffer that provides a reference …

Embodiments disclosed herein provide an apparatus com prising a clock generation circuit
configured to generate a first signal for a first time period and a second signal for a second …

Apparatuses for controlling latencies on input signal paths in semiconductor devices are
disclosed. An example apparatus includes: a clock input buffer that provides a reference …

A semiconductor apparatus including a pipe latch is provided. The pipe latch includes a first
latch unit, a second latch unit and an output unit. The first latch unit configured to store an …

Apparatuses and methods for indirect phase variation detection are disclosed herein. An
example apparatus may include a clock generator circuit comprising a delay-locked loop …

Apparatuses and methods related to adjusting a delay of a command signal path are
disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that …