Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof
M Tsutsumi, K Kajiwara, RS Makala - US Patent 9,991,277, 2018 - Google Patents
A memory opening can be formed through an alternating stack of insulating layers and
sacrificial material layers over a substrate. A material layer stack containing, from outside to …
sacrificial material layers over a substrate. A material layer stack containing, from outside to …
Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
K Miyata, Z Lu, A Lin, D Mao, J Yu, J Alsmeier… - US Patent …, 2016 - Google Patents
2016-01-13 Assigned to SANDISK TECHNOLOGIES INC. reassignment SANDISK
TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof
A Nishida - US Patent 10,283,493, 2019 - Google Patents
A first die includes a three-dimensional memory device and first copper pads. A second die
includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …
includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
KH Kim, M Higashitani, F Toyama… - US Patent 10,510,738, 2019 - Google Patents
2019-01-15 Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same
A Serov, JK Kai, Y Zhang, H Chien… - US Patent 9,728,546, 2017 - Google Patents
(57) ABSTRACT A three dimensional NAND device includes a common vertical channel and
electrically isolated control gate elec trodes on different lateral sides of the channel in each …
electrically isolated control gate elec trodes on different lateral sides of the channel in each …
Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
R Sharangpani, RS Makala, S Kanakamedala… - US Patent …, 2017 - Google Patents
A memory opening can be formed through an alternating stack of insulating layers and
sacrificial material layers provided over a substrate. Annular etch stop material portions are …
sacrificial material layers provided over a substrate. Annular etch stop material portions are …
Passive devices for integration with three-dimensional memory devices
M Nishikawa, R Honma, T Miwa, M Matsumoto… - US Patent …, 2017 - Google Patents
A three dimensional memory device includes a memory device region containing a plurality
of non-volatile memory devices, a peripheral device region containing active driver circuit …
of non-volatile memory devices, a peripheral device region containing active driver circuit …
Method of forming a staircase in a semiconductor device using a linear alignment control feature
Z Lu, J Yu, K Miyata, M Yoshida, J Alsmeier… - US Patent …, 2018 - Google Patents
A linear mark extending perpendicular to a primary step direction of stepped terrace for a
three-dimensional memory device can be employed as a reference feature for aligning a …
three-dimensional memory device can be employed as a reference feature for aligning a …
Passive devices for integration with three-dimensional memory devices
M Nishikawa, R Honma, T Miwa, H Koketsu… - US Patent …, 2017 - Google Patents
A three dimensional memory device includes a memory device region containing a plurality
of non-volatile memory devices, a peripheral device region containing active driver circuit …
of non-volatile memory devices, a peripheral device region containing active driver circuit …
Three-dimensional memory device having passive devices at a buried source line level and method of making thereof
S Shimizu, H Ogawa, Y Kasagi, K Kitamura - US Patent 9,876,031, 2018 - Google Patents
(57) ABSTRACT A layer stack including a lower semiconductor layer, a lower dielectric
layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer …
layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer …