Machine learning based routing congestion prediction in FPGA high-level synthesis
High-level synthesis (HLS) shortens the development time of hardware designs and enables
faster design space exploration at a higher abstraction level. Optimization of complex …
faster design space exploration at a higher abstraction level. Optimization of complex …
[PDF][PDF] Enhancing FPGA Placement Quality via Machine Learning
H Szentimrey - 2020 - atrium.lib.uoguelph.ca
Placement is one of the most important steps in the Field Programmable Gate Array (FPGA)
design flow. However, placement is an NP-hard problem and time-consuming, therefore …
design flow. However, placement is an NP-hard problem and time-consuming, therefore …
[图书][B] Performance-Driven High-Level Synthesis on FPGA: Modeling, Optimization and Application
J Zhao - 2020 - search.proquest.com
The explosion of versatile computation-intensive applications, such as real-time video/image
processing, autonomous driving and artificial intelligence, promotes the rapid development …
processing, autonomous driving and artificial intelligence, promotes the rapid development …