As basic components, optimizing power consumption of flip-flops (FFs) can significantly
reduce the power of digital systems. In this article, an energy-efficient retentive true-single …

The development of in chip manufacturing processes has enhanced energy-efficient nano-
electronic and high-performance devices in daily activities. In recent times, CMOS …

Cryptographic functions for constrained processing environments can be devised using
lightweight cryptography. For use in safety relevant automotive applications where transient …

In this work, we aim to maintain the correct execution of instructions in the pipeline stages.
To achieve that, the integrity for the data computed in registers during execution should be …

Last level cache (LLC), a major contender of chip area, exhibits the highest sensitivity to soft
error. Block reuse prediction is used to exhibit selective protection of LLC blocks. However …

Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to
integration of many cores leading to many challenges such as increased power dissipation …

Integrated circuits have become more vulnerable to soft errors due to smaller transistor sizes
and lower threshold voltage levels. Energy reduction methods make circuits more error …

Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to
integration of many cores leading to many challenges such as increased power dissipation …

Abstract The Von-Neumann bottleneck, a major challenge in computer architecture, results
from significant data transfer delays between the processor and main memory. Crossbar …

The revolution in chip manufacturing processes spanning five decades has proliferated high
performance and energy-efficient nano-electronic devices across all aspects of daily life. In …