Timing error detection is a key technique for resilient circuits to explore the timing margins,
yet it hinders the scan shift operations and increases the excessive test overhead. In this …

In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-
error resilient circuits to reduce the conservative timing guardband induced by process …

Abstract Ternary Quantum-Dot Cellular Automata (TQCA) is a developing nanotechnology
that guarantees lower power utilization and littler size, with quicker speed contrasted with …

To overcome this issue, use Low-Density Parity-Check (LDPC) architecture-based
encryption and decryption, as well as analyses the bus links using Error Correcting Codes …

As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the
clock period are mandatory, to ensure correct circuit behavior under worst-case conditions …

In SoC, every module must function properly even after fabrication. If a module is behaving
properly in terms of it's functionality during the designing of the chip, it must be ensured that …