Over the past four decades, single event upset (SEU) and single event multiple node upset
(SEMNU) have become the major issues in the memory area. Moreover, these upsets are …

The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …

Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of
various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI) …

Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology
reveal the persisting reliability threat single-event latchup (SEL) poses to advanced …

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU)
under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility …

Laser and heavy-ion data reveal the areas and shapes of single-event latchup (SEL)-
sensitive regions in CMOS test structures and their positions relative to the affected pnpn …

Background........................................................................................................................... 46 Neutron-
induced SEL in dual and triple well SRAMs.......................................................... 49 Laser …

Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the
effects of N-and P-well contact densities on single-event latchup. Although scaling has …

This work presents a SEL modeling based on physical simulations performed by MUSCA
SEP3 and electrical simulations. This approach leads to use the layout description and …

A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes,
interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm …