This paper proposes a new dynamic behavior model for single-electron transistors (SETs). A
comprehensive review of modeling techniques and previous models was carried out aiming …

A new macro model of single electron transistor (SET) for SPICE based simulation of SET
circuits is proposed. Two voltage controlled current sources and some scaling factors are …

A novel hybrid silicon Single Electron Transistor Metal Oxide Semiconductor (SETMOS)
logic is evaluated for its functionality and usability. Emphasis is given on obtaining …

This paper presents a design methodology for a single-gate single-electron transistor (SG-
SET) for room temperature operation of SET and hybrid SETMOS circuits. Initially, the SET …

A simple small-signal model of the single-electron transistor is presented. The terminal
voltage variations are considered to be sufficiently small to result in small current variations …

Gordon Moore's" Moore's Law" suggests chip functionality demand doubles every 1.5-2
years, with global semiconductor technology roadmap recommending sub-nanometer …

A methodology to incorporate single-electron transistors (SET) into the IC design flow is
introduced in this paper. A SET model is developed that is defined as a VERILOG-A module …

This study based on Poisson process and orthodox theory of single electron tunneling for
the first time proposes an error probability independent delay model for delay calculation of …

Motivated by the merits of low power dissipation, ultra small size, and high speed of many
nanoelectronic devices, They have been demonstrated to ensure future progress. Single …

Single electron technology is an attractive technology for future low-power VLSI/ULSI
systems. Single electronics implies the possibility to control the movement and position of a …