A data receiver implemented in an integrated circuit is described. The data receiver
comprises an input receiving a data signal; a first equalization circuit coupled to receive the …

BACKGROUND Clock and data recovery (CDR) circuits are used in high speed receivers to
recovertiming information from an incom ing data signal. Many clock and data recovery …

(57) ABSTRACT A data sampler system receives a high-speed data stream and uses a first
set of data samplers for sampling the data stream at a first set of clock phase angles to …

Controller nal include providing a data signal to a differential data input circuit, an offset
control signal, and a strobe pulse. In response to the strobe pulse, the data signal is …

An integrated receiver supports adaptive receive equalization. An incoming bit stream is
sampled using edge and data clock signals derived from a reference clock signal. A phase …

(57) ABSTRACT A receiver is equipped with an adaptive phase-offset control ler and
associated timing-calibration circuitry that together shift the timing for a data sampler and a …

(57) ABSTRACT A method and circuit for performing channel equalization in a high speed
transmission system comprising a transmitter and receiver. An application speci? c digital …

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data
and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol …

2. Description of the Related Art As the processing power of digital computing engines
grows with improvements in technology, and increasingly interconnected networks are …

A decision feedback equalizer (DFE) and method includes summer circuits to add a dynamic
feedback signal representing an h2 tap to a received input and to speculate on an h1 tap …