Development of routing algorithms in networks-on-chip based on ring circulant topologies

AY Romanov - Heliyon, 2019 - cell.com
This work is devoted to the study of communication subsystem of networks-on-chip (NoCs)
development with an emphasis on their topologies. The main characteristics of NoC …

Design of a structured hypercube network chip topology model for energy efficiency in wireless sensor network using machine learning

N Gupta, KS Vaisla, R Kumar - SN Computer Science, 2021 - Springer
Network on chips (NoCs) 3D design expansion is continuously changing to produce energy-
efficient NoCs. In this production, the major requirement is to have continuous monitoring …

[PDF][PDF] Network on chip router for 2D mesh design

A Jain, A Kumar, R Dwivedi, S Sharma - International Journal of …, 2016 - academia.edu
The network version of the multiprocessor system on chip (MPSoC) is called Network on
Chip (NoC). The NoC approach has been proved one of the best techniques for the efficient …

An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

R Poovendran, S Sumathi - Concurrency and computation …, 2019 - Wiley Online Library
The incorporation of network‐on‐Chip with communication delivers a strengthening solution
to the rising complexity and problems in system‐on‐chip. Here, mesh topology is shortly …

A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures

MH Furhad, JM Kim - The Journal of Supercomputing, 2014 - Springer
Network-on-chip-based communication schemes represent a promising solution to the
increasing complexity of system-on-chip problems. In this paper, we propose a new mesh …

Network on Chip for 2D Mesh Toplological Structure in HDL Enviornment

S Kumar, A Kumar, V Rana, V Sharma… - 2023 10th IEEE Uttar …, 2023 - ieeexplore.ieee.org
Network on Chip (NoC) refers to the network variant of the multiprocessor system on chip
(MPSoC). The RoC approach has been demonstrated to be one of the most effective …

[PDF][PDF] An extended diagonal mesh topology for network-on-chip architectures

MH Furhad, JM Kim - International Journal of Multimedia and …, 2015 - researchgate.net
This paper proposes an extended diagonal mesh (XDMesh) topology for network-onchip
(NoC) architectures to reduce latency and energy consumption for fast and lowpower …

L2star: A star type level-2 2d mesh architecture for noc

P Ghosal, TS Das - 2012 Asia Pacific Conference on …, 2012 - ieeexplore.ieee.org
Network topology and related routing policy play an important role to the improvement of
overall performance of an on chip Network (NoC). A structural scalable interconnection …

FL2STAR: A novel topology for on-chip routing in NoC with fault tolerance and deadlock prevention

P Ghosal, TS Das - 2013 IEEE International Conference on …, 2013 - ieeexplore.ieee.org
CMP (Chip Multiprocessor) based architectures have offered a promising solution in
tomorrow's high performance computing demands. Topology and routing policy are playing …

Hamiltonian path strategy for deadlock-free and adaptive routing in diametrical 2D mesh NoCs

P Bahrebar, D Stroobandt - 2015 15th IEEE/ACM International …, 2015 - ieeexplore.ieee.org
The overall performance of Network-on-Chip (NoC) is strongly affected by the efficiency of
the on-chip routing algorithm. Among the factors associated with the design of a high …