RRAM-based analog approximate computing
Approximate computing is a promising design paradigm for better performance and power
efficiency. In this paper, we propose a power efficient framework for analog approximate …
efficiency. In this paper, we propose a power efficient framework for analog approximate …
A 12-bit 40 nm DAC Achieving SFDR> 70 dB at 1.6 GS/s and IMD<–61dB at 2.8 GS/s With DEMDRZ Technique
WT Lin, HY Huang, TH Kuo - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
For current-steering digital-to-analog converters (DACs), a technique utilizing dynamic-
element-matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously …
element-matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously …
A 14 bit 500 MS/s CMOS DAC using complementary switched current sources and time-relaxed interleaving DRRZ
A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and
fabricated in 0.13 μm CMOS process. For traditional wide-band current-steering DACs, the …
fabricated in 0.13 μm CMOS process. For traditional wide-band current-steering DACs, the …
Utilizing multi-body interactions in a CMOS-based ising machine for LDPC decoding
E Elmitwalli, Z Ignjatovic, S Kose - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Ising machines have shown great promise in solving combinatorial optimization problems
(COPs) using nature-inspired computation with higher speed and efficiency over traditional …
(COPs) using nature-inspired computation with higher speed and efficiency over traditional …
Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters
O Morales Chacón, JJ Wikner, C Svensson… - … Integrated Circuits and …, 2022 - Springer
In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio
(SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog …
(SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog …
A 14-bit 1.0-GS/s dynamic element matching DAC with> 80 dB SFDR up to the Nyquist
A 14-bit 1.0-GS/s current-steering digital-to-analog converter (DAC) was designed in a 65-
nm CMOS process. For such current-steering DACs with a high sampling rate, the code …
nm CMOS process. For such current-steering DACs with a high sampling rate, the code …
A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
This article presents a low power high dynamic performance 10-bit Current Steering Digital-
to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based …
to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based …
A 12bit 800MS/s and 1.37 mW Digital to Analog Converter (DAC) based on novel RC technique
S Mahdavi, R Ebrahimi, A Daneshdoust… - … Conference on Power …, 2017 - ieeexplore.ieee.org
This paper presents a novel high-speed and high-resolution Digital to Analog Converter
(DAC) based on new reliable RC technique. In the proposed idea the four Least Significant …
(DAC) based on new reliable RC technique. In the proposed idea the four Least Significant …
Switching sequence optimization for gradient errors compensation in the current-steering DAC design
K Wu, J Li, X Wang, N Ning, K Xu, Q Yu - Microelectronics Journal, 2020 - Elsevier
In this paper, an optimization method of switching sequence is proposed to compensate for
the gradient errors in the current source array of the current-steering digital-to-analog …
the gradient errors in the current source array of the current-steering digital-to-analog …
Design and analysis of a 12-b current-steering DAC in a 14-nm FinFET technology for 2G/3G/4G cellular applications
A 14-nm FinFET CMOS 12-b current-steering digital-to-analog converter (DAC) for
2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer …
2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer …