Exploring the influence of variability on single-electron transistors into SET-based circuits
E Amat, J Bausells… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
We analyze the performance of hybrid single-electron transistor (SET)-FET circuits when
different variability sources are considered, eg, SET's quantum dot location and FET device …
different variability sources are considered, eg, SET's quantum dot location and FET device …
Novel hybrid silicon SETMOS design for power efficient room temperature operation
A novel hybrid silicon Single Electron Transistor Metal Oxide Semiconductor (SETMOS)
logic is evaluated for its functionality and usability. Emphasis is given on obtaining …
logic is evaluated for its functionality and usability. Emphasis is given on obtaining …
Design strategy and simulation of single-gate SET for novel SETMOS hybridization
This paper presents a design methodology for a single-gate single-electron transistor (SG-
SET) for room temperature operation of SET and hybrid SETMOS circuits. Initially, the SET …
SET) for room temperature operation of SET and hybrid SETMOS circuits. Initially, the SET …
Efficient logic architectures for CMOL nanoelectronic circuits
C Dong, W Wang, S Haruehanroengra - Micro & Nano Letters, 2006 - IET
CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC
implementation. Two new CMOL building blocks using transmission gates have been …
implementation. Two new CMOL building blocks using transmission gates have been …
Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits
N-doped polysilicon gated-nanowires (poly-SiNW) are reported. The V-shape and
hysteresis of their IV characteristics are used to build analog and memory circuit cells …
hysteresis of their IV characteristics are used to build analog and memory circuit cells …
[图书][B] Nanoelectronics: Physics, technology and applications
This course text provides comprehensive coverage for fundamental and advanced courses
in nanoelectronics. It provides insight into the future of electronics, emerging devices, logic …
in nanoelectronics. It provides insight into the future of electronics, emerging devices, logic …
A new logic family based on hybrid MOSFET-polysilicon nanowires
A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires
(polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up …
(polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up …
Coulomb blockade in PtSi/porous Si Schottky barrier as a two‐dimensional multi‐tunnelling junction
A Erfanian, H Mehrara, F Raissi… - IET Circuits, Devices & …, 2015 - Wiley Online Library
The authors report on Coulomb blockade effect in the PtSi/porous Si Schottky barrier. A
model of two‐dimensional multi‐tunnelling junction (2D‐MTJ) can explain the blockade …
model of two‐dimensional multi‐tunnelling junction (2D‐MTJ) can explain the blockade …
Electrical conduction in 10 nm thin polysilicon wires from 4 to 400 K and their operation for hybrid memory
S Ecoffey, D Bouvet, S Mahapatra… - Japanese journal of …, 2006 - iopscience.iop.org
This paper reports on the experimental investigation of conduction mechanisms in gated
ultra-thin polysilicon nanowires (polySiNW) over a wide range of temperature: from 4 to 400 …
ultra-thin polysilicon nanowires (polySiNW) over a wide range of temperature: from 4 to 400 …