Benchmarking has become one of the most important methods for quantitative performance evaluation of processor and computer system designs. Benchmarking of modern …
C Bienia, S Kumar, JP Singh, K Li - Proceedings of the 17th international …, 2008 - dl.acm.org
This paper presents and characterizes the Princeton Application Repository for Shared- Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors …
This paper presents a surprising result: changing a seemingly innocuous aspect of an experimental setup can cause a systems researcher to draw wrong conclusions from an …
Locating moving objects in a video sequence is the first step of many computer vision applications. Among the various motion-detection techniques, background subtraction …
D Chandra, F Guo, S Kim… - … Symposium on High …, 2005 - ieeexplore.ieee.org
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a chip multi-processor (CMP) architecture. Cache sharing impacts threads …
Modern processors use two or more levels ofcache memories to bridge the rising disparity betweenprocessor and memory speeds. Compression canimprove cache performance by …
TF Wenisch, RE Wunderlich, M Ferdman… - IEEE Micro, 2006 - ieeexplore.ieee.org
Timing-accurate full-system multiprocessor simulations can take years because of architecture and application complexity. Statistical sampling makes simulation-based …
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's aggregate on-chip cache resources. Cooperative caching combines the strengths of private …
L Yen, J Bobba, MR Marty, KE Moore… - 2007 IEEE 13th …, 2007 - ieeexplore.ieee.org
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transactions read …