Simulation study of dielectric modulated dual channel trench gate TFET-based biosensor

S Kumar, Y Singh, B Singh, PK Tiwari - IEEE Sensors Journal, 2020 - ieeexplore.ieee.org
A dielectric modulated dual channel trench gate tunnel FET (DM-DCTGTFET) based
biosensor is proposed for label-free detection of biomolecules. The gate of DM-DCTGTFET …

GaSb/GaAs Type-II heterojunction TFET on SELBOX Substrate for dielectric modulated label-free biosensing application

AK Singh, MR Tripathy, K Baral… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
A novel GaSb/GaAs type-II heterojunction TFET on SELBOX substrate (HJ-STFET)-based
dielectric-modulated ultrasensitive label-free biosensor has been demonstrated in this …

Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis

P Ghosh, B Bhowmick - … of RF and Microwave Computer‐Aided …, 2020 - Wiley Online Library
This work explores the temperature associated reliability issues of selective buried oxide
(SELBOX) TFET. The proposed device is optimized for maximum ION/IOFF ratio considering …

Optimisation of pocket doped junctionless TFET and its application in digital inverter

WV Devi, B Bhowmick - Micro & Nano Letters, 2019 - Wiley Online Library
In this work, a device called pocket doped junctionless tunnel field‐effect transistor (JL‐
TFET) for digital inverter application is proposed. The operation of this device is subjected to …

Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): introduction to a BG-HJ-STEFT based …

AK Singh, MR Tripathy, K Baral, PK Singh, S Jit - Microelectronics journal, 2020 - Elsevier
This manuscript reports the back-gate effects on device-level performance of a
heterojunction TFET on SELBOX substrate (HJ-STFET). The proposed structure implements …

Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

AK Singh, MR Tripathy, K Baral, PK Singh, S Jit - Applied Physics A, 2020 - Springer
This paper reports the TCAD based investigation of the DC/RF and linearity characteristics
of a newly proposed dual-material (DM) laterally-stacked (LS) SiO 2/HfO 2 heterojunction …

Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

J Talukdar, G Rawat, K Singh… - Journal of Electronic …, 2020 - Springer
This paper investigates the trap analysis of a double-gate extended-source tunnel field-
effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor …

Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance

V Sharma, S Kumar, J Talukdar, K Mummaneni… - Materials Science in …, 2022 - Elsevier
In this paper, we have studied and proposed a planar Tunnel FET device with source side
SiGe pocket and hetero-gate dielectric structure that works by utilizing quantum mechanical …

Enhancement of a nanoscale novel Esaki tunneling diode source TFET (ETDS-TFET) for low-voltage operations

MK Anvarifard, AA Orouji - Silicon, 2019 - Springer
This paper presents a novel nanoscale tunnel FET consisting of an Esaki tunneling diode in
the source region. A unique part of the source region is replaced by a heavily doped N-type …

Characteristic enhancement of hetero dielectric DG TFET using SiGe pocket at source/channel interface: proposal and investigation

SA Sahu, R Goswami, SK Mohapatra - Silicon, 2020 - Springer
This paper reports a method to suppress the ambipolar effect and enhance the on-state
current in Tunnel Field Effect Transistor by exploiting the advantages of Silicon-Germanium …