Timing error prediction circuits have demonstrated greater efficiency in reducing the worst
case timing margins of conventional circuits. However, prior works of timing error prediction …

In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-
error resilient circuits to reduce the conservative timing guardband induced by process …

The impact of variability in CMOS technology increases with scaling and low-voltage
operation, where conventional design flows need to manage large design margins to ensure …

Error detection and correction techniques are conventionally employed in resilient systems
to eliminate timing margins preserved in ICs. However, existing technologies still pose a …

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design.
However, the existing CPR technique cannot accurately reflect the timing of the circuit due to …

In this paper, a low quiescent current power-on-reset circuit with configurable trip voltage is
proposed. With the employment of a 7-transistor configurable voltage reference, the trip …

Latch-based resilient circuits significantly increases the area overhead to address short-path
(SP) issues. This work presents a lowoverhead resilient circuit with partial two-phase latch …