Memory device and erasing and verification method thereof
LI Kaiwei, J Jia, H Liu, A Zhang - US Patent 11,676,665, 2023 - Google Patents
(57) ABSTRACT A memory device includes a memory string and a control circuit coupled to
the memory string. The memory string includes a top select gate, word lines, a bottom select …
the memory string. The memory string includes a top select gate, word lines, a bottom select …
Memory device and erasing and verification method thereof
LI Kaiwei, J Jia, H Liu, A Zhang - US Patent 12,100,456, 2024 - Google Patents
A memory device includes a memory string and a control circuit coupled to the memory
string. The memory string includes a top select gate, word lines, and a bottom select gate …
string. The memory string includes a top select gate, word lines, and a bottom select gate …
Memory device which generates operation voltages in parallel with reception of an address
A Sugahara, T Handa, R Isomura, K Uehara… - US Patent App. 18 …, 2023 - Google Patents
2023-06-05 Assigned to TOSHIBA MEMORY CORPORATION reassignment TOSHIBA
MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
Memory device which generates operation voltages in parallel with reception of an address
A Sugahara, T Handa, R Isomura, K Uehara… - US Patent …, 2023 - Google Patents
A memory device includes a memory cell array, a voltage generation circuit generating one
or more voltages supplied to the memory cell array, an input/output circuit receiving an …
or more voltages supplied to the memory cell array, an input/output circuit receiving an …
Memory device and erasing and verification method thereof
LI Kaiwei, J Jia, H Liu, A Zhang - US Patent 11,158,380, 2021 - Google Patents
A memory device includes a plurality of memory blocks, and a control circuit. A selected
memory block of the plurality of memory blocks comprises a top select gate, a bottom select …
memory block of the plurality of memory blocks comprises a top select gate, a bottom select …
Memory device which generates operation voltages in parallel with reception of an address
A Sugahara, T Handa, R Isomura, K Uehara… - US Patent …, 2022 - Google Patents
US11257551B2 - Memory device which generates operation voltages in parallel with
reception of an address - Google Patents US11257551B2 - Memory device which …
reception of an address - Google Patents US11257551B2 - Memory device which …