Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks
To tackle important combinatorial optimization problems, a variety of annealing-inspired
computing accelerators, based on several different technology platforms, have been …
computing accelerators, based on several different technology platforms, have been …
Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses
Random number generation refers to many applications such as simulation, numerical
analysis, cryptography etc. Field Programmable Gate Array (FPGA) are reconfigurable …
analysis, cryptography etc. Field Programmable Gate Array (FPGA) are reconfigurable …
FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL
AK Panda, P Rajput, B Shukla - 2012 International Conference …, 2012 - ieeexplore.ieee.org
LFSR based PN Sequence Generator technique is used for various cryptography
applications and for designing encoder, decoder in different communication channel. It is …
applications and for designing encoder, decoder in different communication channel. It is …
High-speed area-efficient VLSI architecture of three-operand binary adder
AK Panda, R Palisetty, KC Ray - IEEE Transactions on Circuits …, 2020 - ieeexplore.ieee.org
Three-operand binary adder is the basic functional unit to perform the modular arithmetic in
various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry-save …
various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry-save …
Modified dual-CLCG method and its VLSI architecture for pseudorandom bit generation
AK Panda, KC Ray - … Transactions on Circuits and Systems I …, 2018 - ieeexplore.ieee.org
Pseudorandom bit generator (PRBG) is an essential component for securing data during
transmission and storage in various cryptography applications. Among popular existing …
transmission and storage in various cryptography applications. Among popular existing …
Harnessing intrinsic noise in memristor hopfield neural networks for combinatorial optimization
We describe a hybrid analog-digital computing approach to solve important combinatorial
optimization problems that leverages memristors (two-terminal nonvolatile memories). While …
optimization problems that leverages memristors (two-terminal nonvolatile memories). While …
A coupled variable input LCG method and its VLSI architecture for pseudorandom bit generation
AK Panda, KC Ray - IEEE transactions on instrumentation and …, 2019 - ieeexplore.ieee.org
The dual-coupled-linear congruential generator (LCG)(dual-CLCG) is a secure
pseudorandom bit gene-rator (PRBG) method among various linear feedback shift register …
pseudorandom bit gene-rator (PRBG) method among various linear feedback shift register …
Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number
D Datta, B Datta, HS Dutta - 2017 Devices for Integrated Circuit …, 2017 - ieeexplore.ieee.org
Pseudorandom number generators (PRNGs) are important role in cryptography application.
Hardware based random number generators become faster. Field Programming Gate Arrays …
Hardware based random number generators become faster. Field Programming Gate Arrays …
Efficient hardware implementation of pseudo-random bit generator using dual-CLCG method
MD Gupta, RK Chauhan - Journal of Circuits, Systems and …, 2021 - World Scientific
In this work, the architecture of a dual-coupled linear congruential generator (dual-CLCG) for
pseudo-random bit generation is proposed to improve the speed of the generator and …
pseudo-random bit generation is proposed to improve the speed of the generator and …
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
MD Gupta, RK Chauhan - IET Computers & Digital Techniques, 2021 - Wiley Online Library
The authors present a new method for the generation of pseudorandom bits, based on
coupled variable input linear congruential generator (LCG) and a clock divider. To prevent …
coupled variable input linear congruential generator (LCG) and a clock divider. To prevent …