Wireline IOs have doubled per-lane data-rate every 3-4 years over the last two decades due
to increasing demand in high-performance computing, networking/communications, and …

Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip
integration technology that is widely used in high performance computing (HPC) and …

This article presents analysis, design details, and measurement result of a 224-Gb/s four-
level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage …

This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s
with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero …

A four-level pulse-amplitude modulation (PAM-4) transceiver operating up to 64 Gb/s in 28-
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …

COVID-19 sparked a paradigm shift for businesses, education, and social life. The measures
taken have emphasized, more than ever, the importance of on-line communication …

This article presents a compact analog-to-digital converter (ADC)/digital-to-analog converter
(DAC) digital signal processing (DSP)-based long reach (LR) transceiver in 7-nm FinFET …

This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter
(TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully …

The growing demand for higher data rates in wireline communications has led to emerging
standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have …

To enhance sampling rates of CMOS digital-to-analog converters (DACs), analog
multiplexing of several DAC output signals in the time domain provides a solution. In this …