Future high-performance computing systems will need to include multiple specialized
accelerators in a single heterogeneous system to overcome power-density limitations of …

We describe the support within high-level hardware synthesis (HLS) for two standard
software parallelization paradigms: Pthreads and OpenMP. Parallel code segments, as …

This paper deals with memory partitioning in the context of high-level synthesis for FPGA
technologies. In particular, the work focuses on the area overhead caused by partitioning …

Due to the ubiquity of OpenMP and the rise of FPGA-based accelerators in the HPC world,
several research groups have attempted to bring the two together by building OpenMP-to …

We present an ESL methodology creating a direct path from high-level multi-threaded
OpenMP applications to automatically synthesized, heterogeneous hardware/software …

The choice of the communication topology in many systems is of vital importance because it
affects the entire inter-component data traffic and impacts significantly the overall system …

Abstract Next to GPUs, FPGAs are an attractive target for OpenMP device offloading, as they
allow to implement highly efficient, applications-specific accelerators. However, prior …

This work proposes an automated methodology for optimizing FPGA-based many-core
interconnect architectures. Based on the application communication requirements, the …

FPGAs normally have numerous independent memory banks that can be accessed
simultaneously, potentially offering a very large memory bandwidth. Adopting a suitable …

Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion
but via fine-grained atomic operations ('atomics'), have been shown empirically to be the …