Hardware implementation of memristor-based artificial neural networks
Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL)
techniques, which rely on networks of connected simple computing units operating in …
techniques, which rely on networks of connected simple computing units operating in …
Review of security techniques for memristor computing systems
Neural network (NN) algorithms have become the dominant tool in visual object recognition,
natural language processing, and robotics. To enhance the computational efficiency of these …
natural language processing, and robotics. To enhance the computational efficiency of these …
SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks
G Krishnan, SK Mandal, M Pannala… - ACM Transactions on …, 2021 - dl.acm.org
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic
challenges on area, yield, and on-chip interconnection cost due to the ever-increasing …
challenges on area, yield, and on-chip interconnection cost due to the ever-increasing …
A survey of neuromorphic computing-in-memory: Architectures, simulators, and security
This work is a survey of neuromorphic computing-in-memory. Unlike existing surveys that
focus on hardware or application-level perspectives, the authors elaborate on architectures …
focus on hardware or application-level perspectives, the authors elaborate on architectures …
TxSim: Modeling training of deep neural networks on resistive crossbar systems
Deep neural networks (DNNs) have gained tremendous popularity in recent years due to
their ability to achieve superhuman accuracy in a wide variety of machine learning tasks …
their ability to achieve superhuman accuracy in a wide variety of machine learning tasks …
Impact of on-chip interconnect on in-memory acceleration of deep neural networks
With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms
have evolved in two diverse directions—one with ever-increasing connection density for …
have evolved in two diverse directions—one with ever-increasing connection density for …
Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips
Abstract Computation-in-memory (CIM) chips offer an energy-efficient approach to artificial
intelligence computing workloads. Resistive random-access memory (RRAM)-based CIM …
intelligence computing workloads. Resistive random-access memory (RRAM)-based CIM …
Gibbon: Efficient co-exploration of NN model and processing-in-memory architecture
The memristor-based Processing-In-Memory (PIM) architectures have shown great potential
to boost the computing energy efficiency of Neural Networks (NNs). Existing work …
to boost the computing energy efficiency of Neural Networks (NNs). Existing work …
SAC: An ultra-efficient spin-based architecture for compressed DNNs
Y Zhao, S Ma, H Liu, L Huang, Y Dai - ACM Transactions on Architecture …, 2024 - dl.acm.org
Deep Neural Networks (DNNs) have achieved great progress in academia and industry. But
they have become computational and memory intensive with the increase of network depth …
they have become computational and memory intensive with the increase of network depth …
A non-idealities aware software–hardware co-design framework for edge-AI deep neural network implemented on memristive crossbar
In this work, a non-idealities aware software-hardware co-design framework for deep neural
network (DNN) implemented on memristive crossbar is presented. The device level non …
network (DNN) implemented on memristive crossbar is presented. The device level non …