An example preprocessor circuit includes: a first buffer configured to store rows of image
data and output a row thereof; a second buffer, coupled to the first buffer, including storage …

(57) ABSTRACT A method is described that includes executing a convolu tional neural
network layer on an image processor having an array of execution lanes and a two …

Disclosed herein is a processor for deep learning. In one embodiment, the processor
comprises: a load and store unit configured to load and store image pixel data and stencil …

(57) ABSTRACT A method is described that includes loading an array of content into a two-
dimensional shift register. The two dimensional shift register is coupled to an execution lane …

A method is described that includes executing a convolutional neural network layer on an
image processor having an array of execution lanes and a two-dimensional shift register …

A method is described that includes, on an image processor having a two dimensional
execution lane array and a two dimensional shift register array, repeatedly shifting first …

(57) ABSTRACT A method is described. The method includes repeatedly loading a next
sheet of image data from a first location of a memory into a two dimensional shift register …

A method is described that includes, on an image processor having a two dimensional
execution lane array and a two dimensional shift register array, repeatedly shifting first …

An apparatus is described that include a line buffer unit composed of a plurality of a line
buffer interface units. Each line buffer interface unit is to handle one or more requests by a …

A method is described. The method includes repeatedly loading a next sheet of image data
from a first location of a memory into a two dimensional shift register array. The memory is …