Hardware prefetching is a latency-hiding technique that hides the costly off-chip DRAM
accesses. However, state-of-the-art prefetchers fail to deliver performance improvement in …

Modern processors employ data prefetchers to alleviate the impact of long memory access
latency. However, current prefetchers are designed for specific memory access patterns …

The rowhammer attack on modern DRAM systems is here to stay as the number of row
activations required to induce a DRAM bit flip (rowhammer threshold) is following a trend of …

Coarse-grained reconfigurable arrays (CGRAs) can be dynamically programmed by
configuration contexts to concurrently run multiple operations on a processing elements …

Non-Uniform Cache Architecture (NUCA) is a viable solution to mitigate the problem of large
on-chip wire delay due to the rapid increase in the cache capacity of chip multiprocessors …

This paper proposes a context directed pattern matching (CDPM) mechanism, which
employs the context of the coarse-grained reconfigurable arrays (CGRAs) as a guide to …

Shared-memory, multi-threaded applications often require programmers to insert thread
synchronization primitives (ie locks, barriers, and condition variables) in critical sections to …

In modern multi-core computer architectures, composite prefetching techniques exhibit
promising potential in efficiently handling diverse memory access patterns. However, the …

Abstract The “Memory Wall”, is the gap in performance between the processor and the main
memory. Over the last 30 years computer architects have added multiple levels of cache to …