Uncovering in-dram rowhammer protection mechanisms: A new methodology, custom rowhammer patterns, and implications
The RowHammer vulnerability in DRAM is a critical threat to system security. To protect
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
The reach profiler (reaper) enabling the mitigation of dram retention failures via profiling at aggressive conditions
Modern DRAM-based systems suffer from significant energy and latency penalties due to
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …
Crow: A low-cost substrate for improving dram performance, energy efficiency, and reliability
DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …
trends in multi-core system design and large-dataset applications have amplified the role of …
Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions
DRAM cells require periodic refreshing to preserve data. In JEDEC DDRx devices, a refresh
operation is performed via an auto-refresh command, which refreshes multiple rows in …
operation is performed via an auto-refresh command, which refreshes multiple rows in …
CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off
DRAM is the prevalent main memory technology, but its long access latency can limit the
performance of many workloads. Although prior works provide DRAM designs that reduce …
performance of many workloads. Although prior works provide DRAM designs that reduce …
A case for self-managing dram chips: Improving performance, efficiency, reliability, and security via autonomous in-dram maintenance operations
The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
Another trip to the wall: How much will stacked dram benefit hpc?
M Radulovic, D Zivanovic, D Ruiz… - Proceedings of the …, 2015 - dl.acm.org
First defined two decades ago, the memory wall remains a fundamental limitation to system
performance. Recent innovations in 3D-stacking technology enable DRAM devices with …
performance. Recent innovations in 3D-stacking technology enable DRAM devices with …
Omitting refresh: A case study for commodity and wide i/o drams
Dynamic Random Access Memories (DRAM) have a big impact on performance and
contribute significantly to the total power consumption in systems ranging from mobile …
contribute significantly to the total power consumption in systems ranging from mobile …
Harmony: Heterogeneous-reliability memory and qos-aware energy management on virtualized servers
K Tovletoglou, L Mukhanov, DS Nikolopoulos… - Proceedings of the …, 2020 - dl.acm.org
The explosive growth of data increases the storage needs, especially within servers, making
DRAM responsible for more than 40% of the total system power. Such a reality has made …
DRAM responsible for more than 40% of the total system power. Such a reality has made …