An Architecture for a Tri-Programming Model-Based Parallel Hybrid Testing Tool

SM Altalhi, FE Eassa, ASAM Al-Ghamdi, SA Sharaf… - Applied Sciences, 2023 - mdpi.com
As the development of high-performance computing (HPC) is growing, exascale computing
is on the horizon. Therefore, it is imperative to develop parallel systems, such as graphics …

[PDF][PDF] Software testing techniques for parallel systems: A survey

AM Alghamdi, FE Eassa - Int. J. Comput. Sci. Netw. Secur., 2019 - researchgate.net
Summary High-Performance Computing (HPC) recently has become important in several
sectors, including the scientific and manufacturing fields. The continuous growth in building …

Parallel hybrid testing techniques for the dual-programming models-based programs

AM Alghamdi, FE Eassa, MA Khamakhem… - Symmetry, 2020 - mdpi.com
The importance of high-performance computing is increasing, and Exascale systems will be
feasible in a few years. These systems can be achieved by enhancing the hardware's ability …

[PDF][PDF] Accelerating precise race detection using commercially-available hardware transactional memory support

HS Matar, I Kuru, S Tasiran… - … on Determinism and …, 2014 - wodet.cs.washington.edu
It is typical for state-of-the-art dynamic race detection algorithms for C programs to slow
down an application by a large factor. Our measurements indicate that a significant portion …

Accelerating data race detection utilizing on-chip data-parallel cores

V Mekkat, A Holey, A Zhai - … , RV 2013, Rennes, France, September 24-27 …, 2013 - Springer
Programmers are taking advantage of the increasing availability of on-chip parallelism to
meet the rising performance demands of diverse applications. Support of tools that can …

Parv: Parallelizing runtime detection and prevention of concurrency errors

I Kuru, HS Matar, A Cristal, G Kestor… - Runtime Verification: Third …, 2013 - Springer
We present the PaRV tool for runtime detection of and recovery from data races in multi-
threaded C and C++ programs. PaRV uses transactional memory technology for …

Hardware support for concurrent detection of multiple concurrency bugs on fused cpu-gpu architectures

W Zhang, S Yu, H Wang, Z Dai… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a
cumbersome task for programmers. This situation is further being exacerbated due to the …

Towards Exascale Software Testing

AM Alghamdi - 2019 - kau.edu.sa
High-Performance Computing (HPC) recently has become important in several sectors,
including the scientific and manufacturing fields. The continuous growth in building more …

[PDF][PDF] Efficient storage compression for 3D regions

G Panagopoulou, S Sirmakessis… - Data Compression …, 1997 - Citeseer
In this work we present heuristics algorithms for efficient storage compression for 3D
regions. Giving a 3D decomposed in parallelepipeds, we want to store it using the least …

Hydra: Efficient Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architecture

Z Dai, H Wang, W Zhang, H Chen… - 2014 43rd International …, 2014 - ieeexplore.ieee.org
Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a
cumbersome task for programmers. This situation is further being exacerbated due to the …