A synchronous neural recording platform for multiple high-resolution CMOS probes and passive electrode arrays

GN Angotzi, M Malerba, F Boi, E Miele… - IEEE transactions on …, 2018 - ieeexplore.ieee.org
Electrophysiological signals in the brain are distributed over broad spatial and temporal
scales. Monitoring these signals at multiple scales is fundamental in order to decipher how …

The analysis and application of redundant multistage ADC resolution improvements through PDF residue shaping

J Guerber, M Gande, UK Moon - IEEE Transactions on Circuits …, 2012 - ieeexplore.ieee.org
An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with
redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with …

A high temporal resolution multiscale recording system for in vivo neural studies

GN Angotzi, M Malerba, A Maccione… - … on Circuits and …, 2017 - ieeexplore.ieee.org
Understanding the interplay among the spectrum of electrophysiological signals in the brain,
distributed over broad spatial and temporal scales, is fundamental to decipher how brain …

A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC for X-ray sensor array

Z Zhang, Y Zhang, M Fair, M Zhao, D Liu… - 2016 IEEE …, 2016 - ieeexplore.ieee.org
This paper presents a column-level 14-bit two-stage analog-to-digital converter (ADC)
based on pseudo-differential operational amplifier, which is designed for the readout circuit …

Analysis of integral non-linearity errors in two-step analogue-to-digital converters

G Nikandish, A Medi - IET circuits, devices & systems, 2012 - IET
A new method for modelling and analysis of non-linearity errors caused by the capacitor
mismatches and op-amp non-idealities in two-step analogue-to-digital converters (ADCs) is …

Reduction of substrate noise in sub clock frequency range

SMY Sherazi, S Asif, E Backenius… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
We propose a method of reducing the switching noise in the substrate of an integrated
circuit. The main idea is to design the digital circuits to obtain a periodic supply current with …

Complete time-domain behavioral model of analog to digital converter block using SIMULINK® for advanced RF receiver architectures

F Cannone, G Avitabile, G Coviello… - 2010 17th IEEE …, 2010 - ieeexplore.ieee.org
The paper describes a SIMULINK® model for the complete time-domain behavioral
simulation of A to D converter. In general standard CAD models are lacking in utility, since …

Behavioural models for analog to digital conversion architectures for deep submicron technology nodes

A El-rachini, H Chible, G Nicola… - 2013 25th …, 2013 - ieeexplore.ieee.org
Non-idealities such as static device mismatch and dynamic timing mismatch, in different
architectures of multi-steps analog to digital converter affect the redundancy and …

A low-power 14-bit two-stage hybrid ADC for infrared focal plane array detector

Z Zhang, Y Zhang, M Fan, M Zhao, D Liu… - 2016 IEEE …, 2016 - ieeexplore.ieee.org
This paper presents a low-power 14-bit hybrid incremental Σ-Δ/cyclic analog-to-digital
converter (ADC) based on pseudo-differential operational amplifier, which is designed for …

A 14-bit Hybrid Incremental Sigma-Delta/Cyclic ADC for X-ray Linear Array Sensor

Y Niu, Y Zhang, Z Zhang, M Fan, W Lu, Z Chen - 2017 - preprints.org
This paper presents a two-stage ADC based on pseudo-differential operational
transconductance amplifier (OTA), which is designed for the readout circuit of X-ray linear …