K Shiba, T Omori, K Ueyoshi… - … on Circuits and …, 2020 - ieeexplore.ieee.org
A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling …
J Kadomoto, H Irie, S Sakai - 2019 IEEE 37th International …, 2019 - ieeexplore.ieee.org
Herein, we propose a wireless bus interface that can connect multiple chips to form a flexible system. In the proposed bus interface, on-chip coils are formed along the outer periphery of …
A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling …
E Chong, D Tonietto, Z Xiang - US Patent 10,483,343, 2019 - Google Patents
A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is …
T Ma, Z Xu, L Du, Y Du - 2022 7th International Conference on …, 2022 - ieeexplore.ieee.org
This paper presents a high-speed interconnect of 3D-integrated backside-illuminated (BSI) CMOS image Sensor (CIS) chip by inductive coupling link. With the CIS fusion oxide …