L Forbes, JM Eldridge - US Patent 7,068,544, 2006 - Google Patents
Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second …
JM Eldridge, KY Ahn, L Forbes - US Patent 7,473,956, 2009 - Google Patents
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array …
JM Eldridge, KY Ahn, L Forbes - US Patent 7,135,734, 2006 - Google Patents
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The …
E Gerritsen, N Emonet, C Caillat, N Jourdan… - Solid-State …, 2005 - Elsevier
The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An …
K Kukli, M Ritala, J Sundqvist, J Aarik, J Lu… - Journal of Applied …, 2002 - pubs.aip.org
The interest in depositing dense HfO2 films has increased due to their possible applications as a highpermittivity material that can replace SiO2 in metal–oxide–semiconductor (MOS) …
L Forbes, KY Ahn - US Patent 7,221,586, 2007 - Google Patents
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain …
L Forbes - US Patent 6,754,108, 2004 - Google Patents
Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and …
L Forbes, JM Eldridge, KY Ahn - US Patent 6,952,032, 2005 - Google Patents
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel bar rier intergate insulators are provided. The programmable array …