Rotating semi-batch ALD device

S Murakawa - US Patent 10,480,073, 2019 - Google Patents
The present invention provides a rotating semi-batch ALD device and process which ensure
high productivity, minimal particle formation, low gas consumption and high coverage during …

Flash memory with low tunnel barrier interpoly insulators

L Forbes, JM Eldridge - US Patent 7,068,544, 2006 - Google Patents
Structures and methods for Flash memory with low tunnel barrier intergate insulators are
provided. The non-volatile memory includes a first source/drain region and a second …

Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulators

JM Eldridge, KY Ahn, L Forbes - US Patent 7,473,956, 2009 - Google Patents
Structures and methods for programmable array type logic and/or memory devices with
asymmetrical low tunnel barrier intergate insulators are provided. The programmable array …

Graded composition metal oxide tunnel barrier interpoly insulators

JM Eldridge, KY Ahn, L Forbes - US Patent 7,135,734, 2006 - Google Patents
Structures and methods for programmable array type logic and/or memory devices with
graded composition metal oxide tunnel barrier intergate insulators are provided. The …

Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

E Gerritsen, N Emonet, C Caillat, N Jourdan… - Solid-State …, 2005 - Elsevier
The architecture, materials choice and process technology for stacked-capacitors in
embedded-DRAM applications are a crucial concern for each new technology node. An …

Properties of hafnium oxide films grown by atomic layer deposition from hafnium tetraiodide and oxygen

K Kukli, M Ritala, J Sundqvist, J Aarik, J Lu… - Journal of Applied …, 2002 - pubs.aip.org
The interest in depositing dense HfO2 films has increased due to their possible applications
as a highpermittivity material that can replace SiO2 in metal–oxide–semiconductor (MOS) …

Memory utilizing oxide nanolaminates

L Forbes, KY Ahn - US Patent 7,221,586, 2007 - Google Patents
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided.
One transistor embodiment includes a first source/drain region, a second source/drain …

DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators

L Forbes - US Patent 6,754,108, 2004 - Google Patents
Structures and methods for memory cells having a volatile and a non-volatile component in
a single memory cell are provided. The memory cell includes a first source/drain region and …

Flash memory with low tunnel barrier interpoly insulators

L Forbes, JM Eldridge - US Patent 7,545,674, 2009 - Google Patents
6,534,420 B2 3/2003 Ahn et al. 2001/0041250 A1 11/2001 Werkhoven et al. 6,538,330 B1
3/2003 Forbes 2001/0055838 A1 12/2001 Walker et al................ 438,129 6,541,280 B2 …

Programmable array logic or memory devices with asymmetrical tunnel barriers

L Forbes, JM Eldridge, KY Ahn - US Patent 6,952,032, 2005 - Google Patents
Structures and methods for programmable array type logic and/or memory devices with
asymmetrical low tunnel bar rier intergate insulators are provided. The programmable array …