A review on the design of ternary logic circuits

XY Wang, CT Dong, ZR Wu, ZQ Cheng - Chinese Physics B, 2021 - iopscience.iop.org
A multi-valued logic system is a promising alternative to traditional binary logic because it
can reduce the complexity, power consumption, and area of circuit implementation. This …

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

SU Haq, E Abbasian, VK Sharma, T Khurshid… - … -International Journal of …, 2024 - Elsevier
The appeal of portable electronics, embedded systems, and other smart devices has been
steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle …

Ultra-compact ternary logic gates based on negative capacitance carbon nanotube FETs

MKQ Jooq, MH Moaiyeri… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Ternary logic has been studied for several decades as it can offer significant advantages to
reduce the number of interconnects and the complexity of operations. However, the …

A variation-aware ternary spin-Hall assisted STT-RAM based on hybrid MTJ/GAA-CNTFET logic

F Razi, MH Moaiyeri, R Rajaei… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Magnetic random access memory is a promising solution to keep up with the trend of
memory sizing. On the other hand, the multiple-valued logic has been considered as a …

[HTML][HTML] Ternary encoder and decoder designs in RRAM and CNTFET technologies

SU Haq, VK Sharma - e-Prime-Advances in Electrical Engineering …, 2024 - Elsevier
A possible way for the very large scale integration (VLSI) industry to keep up with the pace of
high density, computational capability, and energy efficiency is to look into some …

Design of high-speed low variation static noise margin ternary S-RAM cells

Y Shrivastava, TK Gupta - IEEE Transactions on Device and …, 2021 - ieeexplore.ieee.org
In this article, two ternary SRAMs are proposed with a lower delay than their predecessor.
Both proposed SRAMs use an improved inverter, which is a fundamental building block of …

Breaking the limits in ternary logic: An ultra-efficient auto-backup/restore nonvolatile ternary flip-flop using negative capacitance CNTFET technology

MH Moaiyeri, MKQ Jooq, A Al-Shidaifat, H Song - IEEE Access, 2021 - ieeexplore.ieee.org
Despite the advantages of ternary logic, it has suffered from excessive transistor count and
limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) …

Design of ternary encoder and decoder using CNTFET

V Prasad, A Banerjee, D Das - International Journal of Electronics, 2022 - Taylor & Francis
Ternary logic emerges as an alternative to the conventional binary logic in designing high
performance, energy-efficient VLSI circuits because it reduces the number of interconnects …

Crosstalk noise analysis of on-chip interconnects for ternary logic applications using FDTD

BD Madhuri, S Sunithamani - Microelectronics Journal, 2019 - Elsevier
This paper presents the crosstalk induced performance analysis of ternary logic coupled on-
chip interconnects using an efficient mathematical model, finite-difference time-domain …

Encapsulation of full adder using 180nm CNTFET

D Manikkule, P Jaronde - 2019 9th International Conference on …, 2019 - ieeexplore.ieee.org
Binary logic is limited to only two states as it is two-valued logic. The ternary logic is the
promising alternative to the conventional binary logic which is also called as trivalent logic …