Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution
S Liu, W Fang, Y Lu, Q Zhang… - 2024 IEEE LLM Aided …, 2024 - ieeexplore.ieee.org
The automatic generation of RTL code (eg, Verilog) using natural language instructions and
large language models (LLMs) has attracted significant research interest recently. However …
large language models (LLMs) has attracted significant research interest recently. However …
Llm for soc security: A paradigm shift
As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic
devices, incorporating security into an SoC design flow poses significant challenges …
devices, incorporating security into an SoC design flow poses significant challenges …
Llm4eda: Emerging progress in large language models for electronic design automation
Driven by Moore's Law, the complexity and scale of modern chip design are increasing
rapidly. Electronic Design Automation (EDA) has been widely applied to address the …
rapidly. Electronic Design Automation (EDA) has been widely applied to address the …
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
Chip design is about to be revolutionized by the integration of large language, multimodal,
and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous …
and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous …
Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms
Assertion-based verification (ABV) is a critical method for ensuring design circuits comply
with their architectural specifications, which are typically described in natural language. This …
with their architectural specifications, which are typically described in natural language. This …
Make every move count: Llm-based high-quality rtl code generation using mcts
M DeLorenzo, AB Chowdhury, V Gohil… - arXiv preprint arXiv …, 2024 - arxiv.org
Existing large language models (LLMs) for register transfer level code generation face
challenges like compilation failures and suboptimal power, performance, and area (PPA) …
challenges like compilation failures and suboptimal power, performance, and area (PPA) …
Specllm: Exploring generation and review of vlsi design specification with large language model
The development of architecture specifications is an initial and fundamental stage of the
integrated circuit (IC) design process. Traditionally, architecture specifications are crafted by …
integrated circuit (IC) design process. Traditionally, architecture specifications are crafted by …
The dawn of ai-native eda: Promises and challenges of large circuit models
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …
as formidable tools, yet they typically augment rather than redefine existing methodologies …
Evolutionary large language models for hardware security: A comparative survey
Automating hardware (HW) security vulnerability detection and mitigation during the design
phase is imperative for two reasons:(i) It must be before chip fabrication, as post-fabrication …
phase is imperative for two reasons:(i) It must be before chip fabrication, as post-fabrication …
OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection
Recent studies have illuminated that Large Language Models (LLMs) exhibit substantial
potential in the realm of RTL (Register Transfer Level) code generation, with notable …
potential in the realm of RTL (Register Transfer Level) code generation, with notable …