High-performance and low-power conditional discharge flip-flop
P Zhao, TK Darwish… - IEEE transactions on very …, 2004 - ieeexplore.ieee.org
In this paper, high-performance flip-flops are analyzed and classified into two categories: the
conditional precharge and the conditional capture technologies. This classification is based …
conditional precharge and the conditional capture technologies. This classification is based …
Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme
In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the
pulse generation control logic, an and function, is removed from the critical path to facilitate a …
pulse generation control logic, an and function, is removed from the critical path to facilitate a …
Low-power pulse-triggered flip-flop design based on a signal feed-through
JF Lin - IEEE transactions on very large scale integration (vlsi) …, 2013 - ieeexplore.ieee.org
In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered
structure and a modified true single phase clock latch based on a signal feed-through …
structure and a modified true single phase clock latch based on a signal feed-through …
Low-power dual dynamic node pulsed hybrid flip-flop featuring efficient embedded logic
K Absel, L Manuel, RK Kavitha - IEEE transactions on very large …, 2012 - ieeexplore.ieee.org
In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel
embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the …
embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the …
Dual-edge triggered storage elements and clocking strategy for low-power systems
N Nedovic, VG Oklobdzija - IEEE Transactions on Very Large …, 2005 - ieeexplore.ieee.org
This paper describes the classification, detailed timing characterization, evaluation, and
design of the dual-edge triggered storage elements (DETSE). The performance and power …
design of the dual-edge triggered storage elements (DETSE). The performance and power …
Clocking and clocked storage elements in a multi-gigahertz environment
VG Oklobdzija - IBM Journal of Research and Development, 2003 - ieeexplore.ieee.org
Clocking considerations and the design of clocked storage elements are discussed in this
paper. We present a systematic approach for deriving a clocked storage element suitable for …
paper. We present a systematic approach for deriving a clocked storage element suitable for …
A fully static true-single-phase-clocked dual-edge-triggered flip-flop for near-threshold voltage operation in IoT applications
A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is
proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET …
proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET …
Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops
A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-
power and high-performance applications is presented in this paper. By incorporating the …
power and high-performance applications is presented in this paper. By incorporating the …
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power
The power efficiency and reducing the layout area are two main concerns in D-Flip-Flops (D-
FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the …
FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the …