Hierarchy multiplier is attractive because of its ability to carry the multiplication operation
within one clock cycle. The existing hierarchical multipliers occupy more area and also …

Abstract We propose three new (4; 2) compressors via improving best previous designs by
replacing an integral portion of relevant logical circuits by an optimized CMOS full-adder …

Recent progress in parallel computing machines, deep neural networks, and training
techniques have contributed to the significant advances in artificial intelligence (AI) with …

Many realisations of multi-operand addition and partial product reduction use (4: 2)
compressor () as the basic addition or reduction cell. A is functionally equivalent to two …

This paper deals with an FPGA implementation of a high performance FM modulator and
demodulator for software defined radio (SDR) system. The individual component of …

(4; 2) compressors seem to be the most popular bit-compressing cells with principal
application in multi-operand addition and multiplication hardware. Therefore, performance of …

A multiplier is a key component in arithmetic and logical units. So low power consuming,
area efficient speedy multiplier architecture is need of today's Arithmetic and Logic Unit. In …

This paper presents an area efficient implementation of a high performance parallel
multiplier. Radix-4 Booth multiplier with 3: 2 compressors and Radix-8 Booth multiplier with …

This paper addresses the design of efficient 2's complement 64-bit array multipliers. We
propose the combination of radix-2 m dedicated multiplier blocks and adder compressors …

This paper presents the implementation and performance comparison of the Booth encoding
technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth …