A survey of architectural approaches for data compression in cache and main memory systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …

DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

Base-delta-immediate compression: Practical data compression for on-chip caches

G Pekhimenko, V Seshadri, O Mutlu… - Proceedings of the 21st …, 2012 - dl.acm.org
Cache compression is a promising technique to increase on-chip cache capacity and to
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …

Memory scaling: A systems architecture perspective

O Mutlu - 2013 5th IEEE International Memory Workshop, 2013 - ieeexplore.ieee.org
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

A large-scale empirical study on self-admitted technical debt

G Bavota, B Russo - Proceedings of the 13th international conference …, 2016 - dl.acm.org
Technical debt is a metaphor introduced by Cunningham to indicate" not quite right code
which we postpone making it right". Examples of technical debt are code smells and bug …

[PDF][PDF] Research problems and opportunities in memory systems

O Mutlu, L Subramanian - Supercomputing frontiers and …, 2014 - superfri.susu.ru
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

Adaptive cache compression for high-performance processors

AR Alameldeen, DA Wood - ACM SIGARCH Computer Architecture …, 2004 - dl.acm.org
Modern processors use two or more levels ofcache memories to bridge the rising disparity
betweenprocessor and memory speeds. Compression canimprove cache performance by …

What your DRAM power models are not telling you: Lessons from a detailed experimental study

S Ghose, AG Yaglikçi, R Gupta, D Lee… - Proceedings of the …, 2018 - dl.acm.org
Main memory (DRAM) consumes as much as half of the total system power in a computer
today, due to the increasing demand for memory capacity and bandwidth. There is a …

Frequent pattern compression: A significance-based compression scheme for L2 caches

A Alameldeen, D Wood - 2004 - minds.wisconsin.edu
With the widening gap between processor and memory speeds, memory system designers
may find cache compression beneficial to increase cache capacity and reduce off-chip …

More on average case vs approximation complexity

M Alekhnovich - 44th Annual IEEE Symposium on Foundations …, 2003 - ieeexplore.ieee.org
We consider the problem to determine the maximal number of satisfiable equations in a
linear system chosen at random. We make several plausible conjectures about the average …