A comprehensive review on microwave FinFET modeling for progressing beyond the state of art

G Crupi, DMMP Schreurs, JP Raskin, A Caddemi - Solid-State Electronics, 2013 - Elsevier
FinFET is a multiple-gate silicon transistor structure that nowadays is attracting an extensive
attention to progress further into the nanometer era by going beyond the downscaling limit of …

Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures

M Shrivastava, M Agrawal, S Mahajan… - … on Electron Devices, 2012 - ieeexplore.ieee.org
We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under
the normal operating condition. Pre-and post failure characteristics are investigated. A …

A thermal-aware device design considerations for nanoscale SOI and bulk FinFETs

US Kumar, VR Rao - IEEE Transactions on Electron Devices, 2015 - ieeexplore.ieee.org
Thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed
in this paper for sub-22-nm technologies using the well-calibrated TCAD simulations. In this …

Experimental assessment of self-heating in SOI FinFETs

AJ Scholten, GDJ Smit, RMT Pijper… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
Experimental assessment of self-heating in SOI FinFETs Page 1 Experimental assessment of
self-heating in SOI FinFETs AJ Scholten, GDJ Smit, RMT Pijper, LF Tiemeijer, HP Tuinhout …

Analytical thermal model for self-heating in advanced FinFET devices with implications for design and reliability

C Xu, SK Kolluri, K Endo… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A rigorous analytical thermal model has been formulated for the analysis of self-heating
effects in FinFETs, under both steady-state and transient stress conditions. 3-D self …

Characterization of self-heating leads to universal scaling of HCI degradation of multi-fin SOI FinFETs

H Jiang, SH Shin, X Liu, X Zhang… - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
SOI FinFETs and other Gate-all-around (GAA) transistors topologies have excellent 3-D
electrostatic control and therefore, have been suggested as potential technology options for …

3D modeling of spatio-temporal heat-transport in III-V gate-all-around transistors allows accurate estimation and optimization of nanowire temperature

MA Wahab, SH Shin, MA Alam - IEEE Transactions on Electron …, 2015 - ieeexplore.ieee.org
Excellent electrostatic control offered by gate-all-around (GAA) geometry makes
multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes …

Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs

H Jiang, N Xu, B Chen, L Zeng, Y He… - Semiconductor …, 2014 - iopscience.iop.org
In this work, the self-heating effect (SHE) on metal gate multiple-fin SOI FinFETs is studied
by adopting the ac conductance technique to extract the thermal resistance and temperature …

An investigation into the comprehensive impact of self-heating and hot carrier injection

Y Liu, Y Ma, Z Yu, S Lou, Y Qu, Y Chang - Electronics, 2022 - mdpi.com
As the device feature size shrinks, the dissipation of power increases and further raises the
carrier and lattice temperature, which finally affects device performance. In this paper, we …

Thermal SPICE modeling of FinFET and BEOL considering frequency-dependent transient response, 3-D heat flow, boundary/alloy scattering, and interfacial thermal …

CC Chung, HH Lin, WK Wan… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
High device density and high power density intensify the self-heating effect in scaled FinFET
circuits to degrade both device and back-end-of-line (BEOL) reliability. The boundary …