FPGA implementation of 8-bit multiplier with reduced delay time

Realization of Resource Efficient Block RAM Based Eight Bit Adder in FPGA

G Dhanabalan, V Karutharaja… - … Techniques in Control …, 2019 - ieeexplore.ieee.org
Delay time of any combinational or sequential circuit realized in field programmable gate
array (FPGA) is the propagation delay of the circuit. Researchers attempt to develop …
被引用次数：19 相关文章

Comparison of multiplication algorithms based on fpga

FW Wibowo - 2018 2nd Borneo International Conference on …, 2018 - ieeexplore.ieee.org
The multiplication algorithm has been widely implemented in many computations and tasks.
In the multiplication algorithm, the multiplication of two numbers has a characteristic of …
被引用次数：11 相关文章
[PDF] researchgate.net

Design of Delay-Efficient Carry-Save Multiplier by Structural Decomposition of Conventional Carry-Save Multiplier

M Venkata Subbaiah… - Intelligent Systems and …, 2022 - Springer
Multiplication is an essential operation in many signal and image processing applications. In
this paper, alternative structures are proposed for binary multiplication using the carry-save …
被引用次数：1 相关文章 所有 3 个版本

FPGA design of SAR type ADC based analog input module for industrial applications

G Dhanabalan, T Murugan - Advances in VLSI and Embedded Systems …, 2021 - Springer
Programmable logic controller (PLC) is connected with analog and digital input and output
modules to process physical variables which are to be maintained at the desired values …
被引用次数：2 相关文章 所有 3 个版本

Design of Delay-Efficient Carry-Save Multiplier by Structural Decomposition of Conventional Carry-Save Multiplier

MV Subbaiah, GU Reddy - Intelligent Systems and Sustainable …, 2022 - books.google.com
Multiplication is an essential operation in many signal and image processing applications. In
this paper, alternative structures are proposed for binary multiplication using the carry-save …
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