This work presents a fully digital background calibration technique of timing mismatch in
time-interleaved analog-to-digital converters (TIADCs). The timing mismatch is estimated by …

Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for
complex, flexible, and robust signal processing algorithms in the digital domain, as well as …

In this research, a second-order delta-sigma modulator (DSM) with 16-bit resolution is
implemented in VHDL and based on FPGA with a time-interleaved (TI) structure. The …

This paper introduces a 3-tap half-rate adaptive decision feedback equalizer (DFE) and a 2-
D eye-opening monitor (EOM). A newly developed regenerating sampler (RG-sampler) with …

The current paper aims at presenting a low-power second-order input-feedforward
continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous …

In this paper, a calibration method aiming at the timing mismatch existing in the TIADC (Time-
Interleaved Analog-to-Digital Converter) is proposed. Monotonicity detecting of the sampled …

A highly linearized open-loop CMOS sample-and-hold is proposed for high-speed and high-
resolution analog-to-digital converters. Thanks to synergistic effects of active and passive …

This paper presents a broadband DC-coupling master-slave sample-and-hold amplifier
(SHA) in 0.13 μm SiGe BiCMOS process. PMOS source follower is implemented as the input …

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better
programmability with different channel characteristics and the possibility of employing …

ABSTRACT A voltage supply scalable analog voltage comparator for a wide input range is
presented in this paper. A digital gate-based methodology is used to design the comparator …