Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

In the coming ubiquitous-IT society, low-power design is one of the key features at which the
VLSI designer should aim. Otherwise, power increase will remain as one of the main …

We propose a novel approach to bus energy minimization that targets crosstalk effects.
Unlike previous approaches, we try to reduce energy through capacitance optimization, by …

Passive shielding has been used to reduce the capacitive coupling effects of adjacent bus
lines by inserting passive ground or power lines (shields) between them. Active shielding is …

As technology scales, the shrinking wire width increases the interconnect resistivity, while
the decreasing interconnect spacing significantly increases the coupling capacitance. This …

In deep-submicron technology, minimising the propagation delay and power consumption
on buses is the most important design objective in system-on-chip design. In particular, the …

A data-distribution and bus-structure aware methodology for the design of coding schemes
for low-power on-chip and interchip communication is presented. A general class of coding …

The viability of bus interconnection models is explored, using the multiple-valued logic
(MVL) paradigm to reduce the cost and energy consumption of off-chip and on-chip address …

The technological evolution has increased the number of transistors for a given die area
significantly and increased the switching speed from few MHz to GHz range. Such inversely …