Integrating receiver with precharge circuitry
JL Zerbe, BW Garlepp, PS Chau, KS Donnelly… - US Patent …, 2012 - Google Patents
Related US Application Data Primary Examiner—Vibol Tan (74) Attorney, Agent, or Firm—
Morgan, Lewis & Bockius (60) Continuation of application No. 12/624.365, filed on LLP Nov …
Morgan, Lewis & Bockius (60) Continuation of application No. 12/624.365, filed on LLP Nov …
[图书][B] The Electrical Engineering Handbook-Six Volume Set
RC Dorf - 2018 - api.taylorfrancis.com
In two editions spanning more than a decade, The Electrical Engineering Handbook stands
as the definitive reference to the multidisciplinary field of electrical engineering. Our …
as the definitive reference to the multidisciplinary field of electrical engineering. Our …
[图书][B] On-chip communication architectures: system on chip interconnect
S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …
increasing complexity of applications, fueled by the era of digital convergence …
Volterra and Wiener equalizers for short-reach 100G PAM-4 applications
N Stojanovic, F Karinou, Z Qiang… - Journal of Lightwave …, 2017 - opg.optica.org
Unlike ultralong coherent optical systems that seriously suffer from fiber nonlinearities, short-
reach noncoherent systems such as data center interconnections, which utilize small, cheap …
reach noncoherent systems such as data center interconnections, which utilize small, cheap …
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell
A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses
and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data …
and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data …
Modeling and analysis of high-speed links
V Stojanovic, M Horowitz - … of the IEEE 2003 Custom Integrated …, 2003 - ieeexplore.ieee.org
Very low bit error rate (BER) requirements for the operation of a high-speed link system
require a very precise analysis of the link performance in order to prevent unrealistic …
require a very precise analysis of the link performance in order to prevent unrealistic …
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
JF Bulzacchelli, M Meghelli, SV Rylov… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To
mitigate the effects of channel loss and other impairments, a 5-tap decision feedback …
mitigate the effects of channel loss and other impairments, a 5-tap decision feedback …
Equalization in high-speed communication systems
J Liu, X Lin - IEEE Circuits and Systems Magazine, 2004 - ieeexplore.ieee.org
The article first discusses the major non-ideal issues of low-cost transmission media for over
Gbps data transmissions-the frequency dispersion loss and channel noise. The former …
Gbps data transmissions-the frequency dispersion loss and channel noise. The former …
Exploring the design space of future CMPs
We study the space of chip multiprocessor (CMP) organizations. We compare the area and
performance trade-offs for CMP implementations to determine how many processing cores …
performance trade-offs for CMP implementations to determine how many processing cores …
Symbol-based signaling device for an electromagnetically-coupled bus system
TD Simon, R Amirtharajah, NJ Marketkar… - US Patent …, 2006 - Google Patents
The present invention provides a chipset for transferring data through an electromagnetically
coupled bus system. The chipset includes a modulator, a matching circuit and a …
coupled bus system. The chipset includes a modulator, a matching circuit and a …